Semiconductor package structure and method for manufacturing the same

A semiconductor package structure, comprising:

• a conductive structure;
• a first semiconductor chip electrically connected to the conductive structure, wherein the first semiconductor chip has a first surface and a second surface opposite to the first surface, the first surface faces the conductive structure, and the first semiconductor chip comprises at least one first conductive element disposed on the second surface;
• a first encapsulant disposed on the conductive structure and covering the first semiconductor chip, wherein the first encapsulant contacts the first conductive element, an upper surface of the first encapsulant is substantially coplanar with an upper surface of the first conductive element, the first encapsulant includes a first portion and a second portion, the first portion is disposed on the second surface of the first semiconductor chip, the second portion covers a lateral surface of the first semiconductor chip, and the first portion and the second portion are formed integrally and concurrently;
• and
• an upper semiconductor chip disposed on the first encapsulant and electrically connected to the first conductive element, wherein the upper semiconductor chip has an active surface facing the conductive structure, and the first semiconductor chip is disposed between the conductive structure and the upper semiconductor chip.

A method for manufacturing a semiconductor package structure, comprising:

• (a) providing a first semiconductor chip, a second semiconductor chip and a conductive structure, wherein the first semiconductor chip and the second semiconductor chip are electrically connected to the conductive structure, the second semiconductor chip is disposed next to the first semiconductor chip, the first semiconductor chip has a first surface and a second surface opposite to the first surface, the first surface faces the conductive structure, the second semiconductor chip has a first surface and a second surface opposite to the first surface, the first surface faces the conductive structure, the first semiconductor chip comprises at least one first conductive element disposed adjacent to the second surface, and the second semiconductor chip comprises at least one second conductive element disposed adjacent to the second surface;
• (b) forming a first encapsulant on the conductive structure to cover the first semiconductor chip, the second semiconductor chip, the first conductive element and the second conductive element, wherein the first encapsulant contacts the first conductive element and the second element, the first encapsulant includes a first portion and a second portion, the first portion is disposed on the second surface of the first semiconductor chip, the second portion covers a lateral surface of the first semiconductor chip, and the first portion and the second portion are formed integrally and concurrently;
• (c) removing a portion of the first encapsulant to expose the first conductive element and the second conductive element;
• and
• (d) disposing an upper semiconductor chip on the first encapsulant to electrically connect the first conductive element and the second conductive element, wherein the upper semiconductor chip has an active surface facing the conductive structure, and the first semiconductor chip is disposed between the conductive structure and the upper semiconductor chip.