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US 11,107,783 B2Granted
Wafer-level package including under bump metal layer
AssigneeSamsung Electronics Co., Ltd.
InventorsHyung Sun Jang, Yeo Hoon Yoon
Life of this patent
Estimating the term…
Abstract
A semiconductor package includes a semiconductor chip comprising a first surface and a second surface, a redistribution layer on the first surface of the semiconductor chip, an under bump metal (UBM) layer on the redistribution layer, and a solder bump on the UBM layer, and the solder bump covers both outer side surfaces of the UBM layer.
Claims18
A wafer-level semiconductor package comprising:
- a semiconductor chip comprising a first surface and a second surface;
- a first passivation layer on the first surface of the semiconductor chip
- a redistribution layer on the first passivation layer;
- a second passivation layer on the first passivation layer and the redistribution layer;
- an under bump metal (UBM) layer on the redistribution layer;
- and
- a solder bump on the UBM layer,
- wherein the solder bump covers both outer side surfaces of the UBM layer and has a bonding surface directly in contact with the second passivation layer,
- wherein a portion of an outer surface of the solder bump extending from the bonding surface forms an acute angle with a bottom surface of the second passivation layer, and
- wherein a thickness of the UBM layer is in a range of 10% to 50% of a thickness of the solder bump.
7 more elements
A wafer-level semiconductor package comprising:
- a semiconductor chip having a connection pad therein;
- a first passivation layer formed on a surface of the semiconductor chip and having a first trench to expose at least a portion of the connection pad;
- a redistribution layer partially covering the first passivation layer and in contact with the connection pad through the trench;
- a second passivation layer having a second trench to expose at least a portion of the redistribution layer;
- an under bump metal (UBM) layer in contact with the at least a portion of the redistribution layer and extending in the second trench and on the second passivation layer;
- and
- a solder bump to cover both outer side surfaces of the UBM layer,
- wherein the solder bump has a bonding surface directly in contact with the second passivation layer,
- wherein a portion of an outer surface of the solder bump extending from the bonding surface forms an acute angle with a bottom surface of the second passivation layer, and
- wherein a thickness of the UBM layer is 40 to 50% of a thickness of the solder bump.
7 more elements
A wafer-level semiconductor package module comprising:
- a main board including a terminal;
- and
- a wafer-level semiconductor package on the main board,
- wherein the wafer-level semiconductor package comprises:
- a semiconductor chip having one surface including a connection pad;
- a first passivation layer configured to cover the one surface of the semiconductor chip;
- a redistribution layer on the first passivation layer;
- a second passivation layer configured to cover the first passivation layer, the second passivation layer including a trench exposing a portion of the redistribution layer;
- an under bump metal (UBM) layer in the trench and on the second passivation layer;
- and
- a solder bump configured to cover both side surfaces of the UBM layer, the solder bump connected to the terminal of the main board,
- wherein the solder bump has a bonding surface directly in contact with the second passivation layer,
- wherein a portion of an outer surface of the solder bump extending from the bonding surface forms an acute angle with a bottom surface of the second passivation layer, and
- wherein a thickness of the UBM layer is 50% of a thickness of the solder bump.
11 more elements
Dependencies are inferred from the claim text.