Back to results
US 11,107,780 B2Granted
Pseudo-stripline using double solder-resist structure
AssigneeIntel Corporation
InventorsLilia May, Robert Alan May, Amruthavalli Pallavi Alur, Robert L. Sankman
Life of this patent
Estimating the term…
Abstract
An integrated-circuit package substrate includes a pseudo-stripline that is shielded below a lower solder-resist layer and an upper solder-resist layer, where an upper shielding plane is sandwiched between the lower and upper solder-resist layers. The lower solder-resist layer can at least partially overlap a landing-pad region of a landing-pad via that penetrates a top build-up layer which is contacted by the lower solder-resist layer.
Claims16
An integrated-circuit package substrate, comprising:
- a lower solder-resist layer on a top build-up layer, wherein the lower solder-resist layer contacts a stripline trace that is between the lower solder-resist, layer and the top build-up layer;
- a lower shielding plane below the top build-up layer, wherein the lower shielding plane covers an X-Y form factor of the stripline trace;
- a conformal metallization film on the lower solder-resist layer, wherein the conformal metallization film forms an upper shielding plane that covers the X-Y form factor of the stripline trace;
- and
- an upper solder-resist layer that covers the conformal metallization film, wherein the upper solder-resist layer is undercut by the conformal metallization film, between the upper solder-resist layer and the lower solder-resist layer.
2 more elements
An integrated-circuit package, comprising:
- an integrated-circuit package substrate;
- a lower solder-resist layer on a top build-up layer of the integrated-circuit package substrate, wherein the lower solder-resist layer contacts a stripline trace that is between the lower solder-resist layer and the top build-up layer;
- a lower shielding plane below the top build-up layer, wherein the lower shielding plane covers an X-Y form factor of the stripline trace;
- a conformal metallization film on the lower solder-resist layer, wherein the conformal metallization film forms an upper shielding plane that covers the X-Y form factor of the stripline trace;
- an upper solder-resist layer that covers the conformal metallization film;
- a landing-pad via that penetrates the top build-up layer;
- a surface finish on the landing-pad via, wherein the conformal metallization film forms an undercut below upper solder-resist layer, and wherein the upper solder-resist layer exposes the surface finish;
- and
- an integrated-circuit die coupled to the landing-pad via by contact through an electrical bump that contacts the integrated-circuit die and the surface finish.
6 more elements
Dependencies are inferred from the claim text.