Integrated electrical/optical interface with two-tiered packaging

A chip package comprising:

• a package substrate having a built-up layer disposed on a core substrate, the built-up layer forming a top surface of the package substrate, a portion of the core substrate exposed to form a notch in the top surface of the package substrate;
• an interposer disposed on the package substrate;
• a first integrated circuit (IC) die mounted on a top surface of the interposer, the first IC die comprising circuitry the first IC die comprises circuitry configured to transmit a plurality of data signals and to transmit a clock signal;
• a second IC die mounted on the top surface of the interposer, the second IC die comprising circuitry configured to receive the data signals transmitted by the first IC die using the clock signal transmitted by the first IC die;
• and
• an optical die mounted in the notch formed in the top surface of the package substrate, the optical die is disposed under a portion of the second IC die;
• wherein the interposer is disposed between the package substrate and the first IC die, the interposer is disposed between the package substrate and the second IC die, the interposer is disposed between the second IC die and the optical die, the interposer having a first surface and a second surface opposite the first surface, the interposer comprising:
• a plurality of first group of routings extending beneath the first surface of the interposer coupling the optical die to the second IC die;
• a plurality of second group of routings extending beneath the first surface of the interposer coupling the first IC die and a bottom surface of the package substrate;
• and
• a plurality of third group of routings disposed through the interposer and coupling a driver circuitry to the circuitry of the second die, the plurality of third group of routings having a routing density that is greater than a routing density of the plurality of first group of routings, the third group of routings configured to transmit signals at a rate slower than signals transmitted on the first group of routings while having a throughput density of at least 2 Tbps/mm and an energy efficiency of less than 1 pJ/bit.