Chip package and manufacturing method thereof

A chip package, comprising:

• a lower substrate;
• a first silicon nitride substrate;
• a bonding layer located between the lower substrate and the first silicon nitride substrate, and made of a material comprising Benzocyclobutene (BCB)
• an upper substrate located on the first silicon nitride substrate;
• a first functional layer located between the upper substrate and the first silicon nitride substrate;
• a transparent conductive layer located on the upper substrate;
• an isolation layer covering the upper substrate and the transparent conductive layer;
• and
• a first conductive pad located in the isolation layer and in electrical contact with the transparent conductive layer, wherein the first conductive pad comprises a titanium nitride layer, a titanium layer, a gold layer, and a silver (Ag) epoxy that are stacked in order.

A manufacturing method of a chip package, comprising:

• forming a transparent conductive layer on an upper substrate of a wafer structure, wherein the wafer structure has a lower substrate, a bonding layer, a first silicon nitride substrate, a first functional layer, and the upper substrate that are stacked in order, wherein the bonding layer is located between the lower substrate and the first silicon nitride substrate, and a material of the bonding layer comprises Benzocyclobutene (BCB);
• forming an isolation layer that covers the upper substrate and the transparent conductive layer;
• forming a first conductive pad in the isolation layer and electrically connected to the transparent conductive layer;
• forming a second conductive pad on the isolation layer, wherein a normal projection of the second conductive pad on the upper substrate is spaced apart from the transparent conductive layer, and the second conductive pad is electrically isolated from the transparent conductive layer;
• and
• cutting the wafer structure to form a chip package.