Packaging for lateral high voltage GaN power devices
OwnerZhanming Li, Yue Fu +1inventors
InventorsZhanming Li, Yue Fu, Yan-Fei Liu
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Abstract
Packaging methods and structures for lateral high voltage gallium nitride (GaN) devices achieve electrical isolation while also maintaining thermal dissipation. The electrical isolation reduces or eliminates vertical leakage current, improving high voltage performance. The packages may use or be compatible standards such as JEDEC, which reduces packaging cost and facilitates implementation of the packaged devices in conventional circuit design approaches.
Claims22
A packaged semiconductor device, comprising:
- a lateral semiconductor power device chip comprising an upper surface having at least two electrodes disposed thereon, and a lower surface, wherein the upper and lower surfaces are coplanar;
- at least one metal lead electrically connected to a first electrode of the at least two electrodes;
- a back-plate;
- an electrically insulating and thermally conducting adhesive disposed between the lower surface of the lateral semiconductor power device chip and the back-plate;
- wherein the back-plate comprises at least a metal portion that is electrically connected to a second electrode of the at least two electrodes.
A method for packaging a lateral semiconductor power device chip comprising an upper surface having at least two electrodes disposed thereon, and a lower surface, wherein the upper and lower surfaces are coplanar, the method comprising:
- electrically connecting a first electrode of the at least two electrodes to a first metal lead of a device package;
- disposing an electrically insulating and thermally conducting adhesive between the lower surface of the lateral semiconductor power device chip and a back-plate of the device package;
- wherein the back-plate comprises at least a metal portion that is electrically connected to a second electrode of the at least two electrodes.
Dependencies are inferred from the claim text.