Half buried nFET/pFET epitaxy source/drain strap

A method for reducing parasitic capacitance, the method comprising:

• forming nanosheet stacks including alternating layers of a first semiconductor material and a second semiconductor material over a substrate (10);
• depositing a dummy gate over the nanosheet stacks;
• forming a p-type epitaxial region and an n-type epitaxial region adjacent each of the nanosheet stacks;
• depositing an epitaxial growth over the p-type epitaxial region and the n-type epitaxial region;
• depositing a first dielectric between the p-type epitaxial region and the n-type epitaxial region such that an airgap is defined therebetween;
• selectively removing the epitaxial growth to expose top surfaces of the p-type and n-type epitaxial regions;
• depositing a second dielectric in direct contact with the exposed top surfaces of the p-type and n-type epitaxial regions;
• removing the dummy gate and the first semiconductor material of the nanosheet stacks resulting in openings;
• depositing a high-k metal gate within the openings;
• selectively etching the first and second dielectrics to form a strapped contact;
• and
• applying a metallization layer over the strapped contact.