Face-to-face through-silicon via multi-chip semiconductor apparatus with redistribution layer packaging and methods of assembling same
AssigneeIntel Corporation
InventorsLoke Yip Foo, Choong Kooi Chee
Life of this patent
Estimating the term…
Abstract
Reduced-profile semiconductor device apparatus are achieved by thinning a semiconductive device substrate at a backside surface to expose a through-silicon via pillar, forming a recess to further expose the through-silicon via pillar, and by seating an electrical bump in the recess to contact both the through-silicon via pillar and the recess. In an embodiment, the electrical bump contacts a semiconductor package substrate to form a low-profile semiconductor device apparatus. In an embodiment, the electrical bump contacts a subsequent die to form a low-profile semiconductor device apparatus.
Claims21
A semiconductor apparatus, comprising:
- a first semiconductive device including an active surface and a backside surface;
- a through-silicon via (TSV) that communicates from the active surface to the backside surface;
- first and second electrical bumps coupled to the active surface;
- subsequent and second semiconductive devices in respective contact with the first and second electrical bumps, wherein the subsequent and second semiconductive devices are positioned face-to-face with the first semiconductive device;
- and
- a redistribution layer (RDL) including at least one inner via in direct contact with the first semiconductive device backside surface and the TSV.
A computing system, comprising:
- a first semiconductive device including an active surface and a backside surface;
- a through-silicon via (TSV) that communicates from the active surface to the backside surface;
- first and second electrical bumps coupled to the active surface;
- subsequent and second semiconductive devices in respective contact with the first and second electrical bumps, wherein the subsequent and second semiconductive devices are positioned face-to-face with the first semiconductive device;
- a redistribution layer (RDL) including at least one inner via in direct contact with the first semiconductive device backside surface and the TSV;
- a molding compound that contacts the respective first and second electrical bumps, wherein the first and second electrical bumps are copper pillars;
- wherein the TSV is a first TSV and wherein the first TSV is positioned below the subsequent semiconductive device;
- a second TSV that communicates from the active surface to the backside surface, wherein the second TSV is positioned below the second semiconductive device;
- wherein the first semiconductive device exhibits a die shadow, wherein the RDL is configured substantially within the die shadow, and wherein each of the subsequent and second semiconductive devices are configured within the die shadow;
- and
- wherein the semiconductor apparatus is part of a chipset.
A semiconductor apparatus, comprising:
- a first semiconductive device including an active surface and a backside surface;
- a first throutth-silicon via (TSV) that communicates from the active surface to the backside surface;
- a second TSV that communicates from the active surface to the backside surface, wherein the first TSV is positioned below a subsequent semiconductive device, and wherein the second TSV is positioned below a second semiconductive device;
- first and second electrical bumps coupled to the active surface;
- the subsequent and second semiconductive devices in respective contact with the first and second electrical bumps, wherein the subsequent and second semiconductive devices are positioned face-to-face with the first semiconductive device;
- a redistribution layer (RDL) including at least one inner via in direct contact with the first semiconductive device backside surface and the first and second TSVs;
- and
- wherein the first semiconductive device exhibits a die shadow, wherein the RDL is configured substantially within the die shadow, and wherein each of the subsequent and second semiconductive devices are configured within the die shadow.
Dependencies are inferred from the claim text.