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US 11,107,740 B2Granted
Power semiconductor module
AssigneeABB Power Grids Switzerland AG
InventorsJürgen Schuderer, Umamaheswara Vemulapati, Marco Bellini, Jan Vobecky
Life of this patent
Estimating the term…
Abstract
A power semiconductor module including at least one power semiconductor chip providing a power electronics switch; and a semiconductor wafer, to which the at least one power semiconductor chip is bonded; wherein the semiconductor wafer is doped, such that it includes a field blocking region and an electrically conducting region on the field blocking region, to which electrically conducting region the at least one power semiconductor chip is bonded.
Claims23
A power semiconductor module, comprising:
- a semiconductor wafer;
- a first power semiconductor chip having a bottom surface attached to a front side of the semiconductor wafer, the first power semiconductor chip comprising a power electronics switch that has a vertical current path between a top surface of the first power semiconductor chip and the bottom surface, the top surface being opposite the bottom surface;
- a second power semiconductor chip attached to the front side of the semiconductor wafer and laterally spaced from the first power semiconductor chip;
- wherein the semiconductor wafer comprises a field blocking region and an electrically conducting region;
- wherein the electrically conducting region is formed on the field blocking region;
- wherein the first power semiconductor chip is bonded to the electrically conducting region;
- and
- wherein the field blocking region extends across the semiconductor wafer beneath both the first power semiconductor chip and the second power semiconductor chip, the electrically conducting region being separated from a back side of the semiconductor wafer by the field blocking region, the back side being opposite the front side.
5 more elements
A power semiconductor module, comprising:
- a semiconductor wafer;
- a first power semiconductor chip having a bottom side attached to a front side of the semiconductor wafer, the first power semiconductor chip comprising a power electronics switch that has a current path between a top side of the first power semiconductor chip and the bottom side, the top side being opposite the bottom side;
- a second power semiconductor chip attached to the front side of the semiconductor wafer and laterally spaced from the first power semiconductor chip;
- a DC+ conducting region doped into the semiconductor wafer, wherein the first power semiconductor chip is bonded to the DC+ conducting region;
- a first field mitigation structure doped into the semiconductor wafer, the DC+ conducting region being surrounded by the first field mitigation structure;
- an AC conducting region doped into the semiconductor wafer, wherein the second power semiconductor chip is bonded to the AC conducting region and wherein the AC conducting region is electrically connected to the top side of the first power semiconductor chip;
- a second field mitigation structure doped into the semiconductor wafer, the AC conducting region being surrounded by the second field mitigation structure;
- and
- a DC− metallization layer electrically connected to a top side of the second power semiconductor chip.
6 more elements
A power semiconductor module, comprising:
- a semiconductor wafer;
- a first power semiconductor chip attached to a front side of the semiconductor wafer, the first power semiconductor chip comprising a power electronics switch;
- a second power semiconductor chip attached to the front side of the semiconductor wafer and laterally spaced from the first power semiconductor chip;
- a DC+ conducting region doped into the semiconductor wafer, wherein the first power semiconductor chip is bonded to the DC+ conducting region;
- a first field mitigation structure doped into the semiconductor wafer, the DC+ conducting region being surrounded by the first field mitigation structure;
- a DC− conducting region, wherein the second power semiconductor chip is bonded to the DC− conducting region in a reverse direction with respect to a connection of the first power semiconductor chip to the DC+ conducting region;
- an AC conducting region doped into the semiconductor wafer electrically connected to a top side of the first power semiconductor chip and to a top side of the second power semiconductor chip;
- and
- a second field mitigation structure doped into the semiconductor wafer, the AC conducting region being surrounded by the second field mitigation structure.
6 more elements
Dependencies are inferred from the claim text.