Power semiconductor module arrangement

A power semiconductor module arrangement, comprising:

• a first switching element and a second switching element, each having a control terminal and a controllable load path between two load terminals, the load path of the first switching element and the load path of the second switching element being operatively coupled in series and between a first supply node which is configured to be operatively coupled to a first electrical potential, and a second supply node which is configured to be operatively coupled to a second electrical potential, wherein the first switching element and the second switching element are connected with each other via a first common node;
• and
• an output node configured to be coupled to an output potential, the output node being coupled to the first common node,
• wherein the first supply node is formed by a plurality of first terminals,
• wherein the second supply node is formed by a plurality of second terminals,
• wherein the output node is formed by a plurality of third terminals,
• wherein a first auxiliary emitter terminal of the first switching element is electrically coupled to the control terminal of the first switching element,
• wherein a second auxiliary emitter terminal of the second switching element is electrically coupled to the control terminal of the second switching element,
• wherein the first switching element and the second switching element are arranged inside a housing, the housing comprising a first longitudinal side, a second longitudinal side, a first narrow side, and a second narrow side,
• wherein the first terminals are at least partly arranged in a first section of the housing adjacent to the first narrow side,
• wherein the third terminals, the first control terminal, a first emitter terminal and the first auxiliary emitter terminal are arranged in a third section of the housing adjacent to the second narrow side,
• wherein the second terminals, the second control terminal, a second emitter terminal, and the second auxiliary emitter terminal are arranged in a second section of the housing which is arranged between the first section and the third section.