Gate structures for semiconductor devices

A method, comprising:

• forming first and second fin structures of n-type field effect transistors (NFETs) and p-type FETs (PFETs), respectively;
• forming first and second nanostructured channel regions in the first and second fin structures, respectively;
• depositing a high-K gate dielectric layer surrounding the first and second nanostructured channel regions;
• selectively forming a first rare-earth metal (REM)-based layer on first and second portions of the high-K gate dielectric layer on the first and second nanostructured channel regions;
• performing a first anneal process on the first REM-based layer;
• selectively forming a second REM-based layer on the first portions of the high-K gate dielectric layer and third portions of the high-K gate dielectric layer on the first and second nanostructured channel regions;
• performing a second anneal process on the second REM-based layer;
• depositing a work function metal layer on the high-K gate dielectric layer;
• and
• depositing a gate metal fill layer on the work function metal layer.

A semiconductor device, comprising:

• a first gate structure comprising:
• a first interfacial oxide layer;
• a first high-K gate dielectric layer with a first rare-earth metal (REM) oxide dopant concentration disposed on the first interfacial oxide layer, and
• a first dipole layer with a first REM dipole concentration disposed at an interface between the first interfacial oxide layer and the first high-K gate dielectric layer,
• a second gate structure comprising:
• a second interfacial oxide layer,
• a second high-K gate dielectric layer with a second REM oxide dopant concentration disposed on the second interfacial oxide layer, and
• a second dipole layer with a second REM dipole concentration disposed at an interface between second first interfacial oxide layer;
• and
• a third gate structure comprising:
• a third interfacial oxide layer,
• a third high-K gate dielectric layer with a third REM oxide dopant concentration disposed on the third interfacial oxide layer, and
• a third dipole layer with a third REM dipole concentration disposed at an interface between the third interfacial oxide layer and the first high-K gate dielectric layer,
• wherein the first, second, and third REM oxide dopant concentrations are different from each other, and
• wherein the first, second, and third REM dipole concentrations are different from each other.