Multi-dimensional planes of logic and memory formation using single crystal silicon orientations

A method of forming 3D transistor devices, the method comprising:

• forming a first transistor plane on a substrate, the first transistor plane including at least one layer of field effect transistors;
• depositing a first insulator layer on the first transistor plane;
• forming holes that extend partially into the first insulator layer using a first etch mask;
• depositing a first layer of polycrystalline silicon on the first insulator layer, the first layer of polycrystalline silicon filling the holes and covering the first insulator layer;
• forming a first relief pattern on the first layer of polycrystalline silicon, the first relief pattern defining openings of a first geometry that uncover first portions of the first layer of polycrystalline silicon;
• depositing a first metal on the substrate, the first metal being deposited within the defined openings of the first relief pattern and adopting the first geometry such that depositions of the first metal having the first geometry are in contact with the first layer of polycrystalline silicon;
• thermally annealing the first layer of polycrystalline silicon, the first metal having the first geometry inducing crystallization of silicon of a first orientation within the holes;
• planarizing the substrate down to a top surface of the first insulator layer;
• depositing a second layer of polycrystalline silicon on the first insulator layer, the second layer of polycrystalline silicon being in contact with crystallized silicon filling the holes;
• annealing the second layer of polycrystalline silicon using laser heating, the laser heating creating regions of single-crystal silicon having the first orientation above the first transistor plane;
• and
• forming a second transistor plane in the created regions of single-crystal silicon.