Self-aligned repaired top via

A method for fabricating a semiconductor device, comprising:

• forming conductive material on a first metallization level including at least one via disposed on at least one conductive line;
• subtractively patterning the conductive material to form at least one conductive layer corresponding to at least one conductive line of a second metallization level misaligned with the at least one via of the first metallization level, and a cavity within the at least one via forming at least one damaged via resulting from the misalignment;
• selectively growing conductive liner material on exposed conductive material including within the at least one cavity to form at least one filled cavity;
• and
• removing portions of the conductive liner material except for the at least one filled cavity and portions of the conductive liner material on sidewalls of the at least one conductive layer to repair the at least one damaged via.

A semiconductor device, comprising:

• a first metallization level including a reduced sized via disposed on a first conductive line within a first interlevel dielectric (ILD) layer, the reduced sized via including a cavity adjacent to the first ILD layer;
• a second metallization level including a second conductive line within a second interlevel dielectric (ILD) layer coupled to the reduced sized via;
• and
• conductive liner material along a sidewall of the second conductive line extending into the cavity to form a filled cavity to permit the reduced sized via to function as a full sized via.