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US 11,107,728 B2Granted
Interconnects with tight pitch and reduced resistance
AssigneeInternational Business Machines Corporation
InventorKangguo Cheng
Life of this patent
Estimating the term…
Abstract
Integrated chips and methods of forming conductive lines thereon include forming parallel lines from alternating first and second dummy materials. Portions of the parallel lines are etched, using respective selective etches for the first and second dummy materials, to form gaps. The gaps are filled with a dielectric material. The first and second dummy materials are etched away to form trenches. The trenches are filled with conductive material.
Claims13
A method of forming conductive lines, comprising:
- forming parallel lines from alternating first and second dummy materials;
- etching portions of the parallel lines, using respective selective etches for the first and second dummy materials, to form gaps;
- filling the gaps with a dielectric material;
- etching away the first and second dummy materials to form trenches;
- and
- filling the trenches with conductive material.
3 more elements
A method of forming conductive lines, comprising:
- forming a via that penetrates a dielectric layer;
- filling the via with a first dummy material;
- forming parallel lines on the dielectric layer from alternating first and second dummy materials;
- etching portions of the parallel lines, using respective selective etches for the first and second dummy materials, to form gaps;
- filling the gaps with a dielectric material;
- etching away the first and second dummy materials to form trenches;
- and
- filling the trenches and the via with conductive material.
5 more elements
Dependencies are inferred from the claim text.