3D semiconductor device and structure with NAND logic

A 3D semiconductor device, the device comprising:

• a first level comprising a single crystal layer and a plurality of first transistors;
• a first metal layer comprising interconnects between said plurality of first transistors,
• wherein said interconnects between said plurality of first transistors comprises forming a plurality of logic gates;
• a plurality of second transistors atop at least a portion of said first metal layer,
• wherein at least six of said plurality of first transistors are connected in series forming at least a portion of a NAND logic structure,
• wherein said plurality of second transistors are vertically oriented transistors, and
• wherein said plurality of second transistors are at least partially directly atop said NAND logic structure;
• and
• a second metal layer atop at least a portion of said plurality of second transistors,
• wherein said second metal layer is aligned to said first metal layer with less than 150 nm misalignment,
• wherein a via connects from at least one of said second transistors to at least one of said NAND logic structure, and
• wherein at least one of said second transistors is a junction-less transistor.

A 3D semiconductor device, the device comprising:

• a first level comprising a single crystal layer and a plurality of first transistors;
• a first metal layer comprising interconnects between said plurality of first transistors,
• wherein said interconnects between said plurality of first transistors comprises forming a plurality of logic gates;
• a plurality of second transistors atop at least a portion of said first metal layer,
• wherein at least six of said plurality of first transistors are connected in series forming at least a portion of a NAND logic structure,
• wherein said plurality of second transistors are vertically oriented transistors, and
• wherein said plurality of second transistors are at least partially directly atop of said NAND logic structure;
• and
• a second metal layer atop at least a portion of said plurality of second transistors,
• wherein said second metal layer is aligned to said first metal layer with less than 150 nm misalignment, and
• wherein at least one of said second transistors is a junction-less transistor.