Methods for manufacturing semiconductor devices
AssigneeSamsung Electronics Co., Ltd.
InventorsJung Han Lee, Byoung-gi Kim, Jong Pil Kim, Kihwan Lee
Life of this patent
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Abstract
A method for manufacturing a semiconductor device includes performing a first ion implantation process on a substrate to form a lower dopant region in the substrate, patterning the substrate having the lower dopant region to form active patterns, and performing a second ion implantation process on the active patterns to form an upper dopant region in an upper portion of each of the active patterns. The lower and upper dopant regions have a same conductivity type.
Claims20
A method for manufacturing a semiconductor device, the method comprising:
- performing a first ion implantation process on a substrate to form a lower dopant region;
- performing a second ion implantation process on the substrate to form an anti-punch through region on the lower dopant region;
- forming mask patterns on the substrate, the mask patterns defining covered portions and uncovered portions;
- etching the uncovered portions using the mask patterns as etch masks to form trenches extending into the lower dopant region and defining discrete fins;
- and
- forming a device isolation layer in the trenches between the discrete fins,
- wherein the lower dopant region and the anti-punch through region have a same conductivity type, and
- wherein a concentration of dopants of the anti-punch through region is higher than a concentration of dopants of the lower dopant region.
A method for manufacturing a semiconductor device, the method comprising:
- performing a first ion implantation process on a substrate to form a lower dopant region;
- performing a second ion implantation process on the substrate to form an anti-punch through region on the lower dopant region;
- forming mask patterns on the substrate, the mask patterns defining covered portions and uncovered portions;
- etching the uncovered portions using the mask patterns as etch masks to form trenches extending into the lower dopant region and defining discrete fins;
- forming a device isolation layer in the trenches between the discrete fins;
- and
- forming a gate electrode on an upper portion of respective ones of the discrete fins,
- wherein the first ion implantation process is performed at a higher power than the second ion implantation process.
A method for manufacturing a semiconductor device, the method comprising:
- forming a first lower dopant region and a second lower dopant region in a PMOSFET region and a NMOSFET region of a substrate, respectively;
- forming a first anti-punch through region and a second anti-punch through region on the first lower dopant region and the second lower dopant region, respectively;
- patterning the PMOSFET region and the NMOSFET region to form a first fin and a second fin, respectively;
- and
- forming a first source/drain pattern and a second source/drain pattern in upper portions of the first fin and the second fin, respectively;
- and
- forming a device isolation layer between the first fin and the second fin,
- wherein a conductivity type of the first source/drain pattern is different from a conductivity type of the first anti-punch through region, and
- wherein a conductivity type of the second source/drain pattern is different from a conductivity type of the second anti-punch through region.
Dependencies are inferred from the claim text.