Mask assembly and method for fabricating a chip package

A method for fabricating conductive wirings, comprising:

• patterning a photoresist layer, comprising:
• providing a first mask comprising a first alignment pattern and a first layout pattern;
• performing a first exposure process via the first mask and a first development process to form a first alignment opening and a plurality of first wiring openings in a first portion of the photoresist layer, and the first portion of the photoresist layer being covered by the first mask;
• providing a second mask comprising a second alignment pattern and a second layout pattern;
• performing a second exposure process via the second mask and a second development process to form a plurality of second wiring openings in a second portion of the photoresist layer, an overlay portion of the first portion and the second portion of the photoresist layer being covered by the second mask, and the second alignment pattern of the second mask being substantially aligned with the first alignment opening formed in the photoresist layer when performing the second exposure process;
• forming an alignment mark in the first alignment opening;
• and
• forming the conductive wirings in the first wiring openings and the second wiring openings.

A method for fabricating a chip package, comprising:

• forming an insulating encapsulation to laterally encapsulate sidewalls of at least one integrated circuit component;
• forming a conductive layer on the at least one integrated circuit component and the insulating encapsulation;
• forming a photoresist layer on the conductive layer and performing a multi-step exposure and development process to pattern the photoresist layer, wherein performing the multi-step exposure and development process to pattern the photoresist layer comprises:
• providing a first mask comprising a first alignment pattern and a first layout pattern;
• performing a first step exposure process via the first mask and a first development process to form a first alignment opening and a plurality of first wiring openings in a first portion of the photoresist layer, and the first portion of the photoresist layer being covered by the first mask;
• providing a second mask comprising a second alignment pattern and a second layout pattern;
• performing a second step exposure process via the second mask and a second development process to form a plurality of second wiring openings in a second portion of the photoresist layer, a part of the first portion and the second portion of the photoresist layer being covered by the second mask, and the second alignment pattern of the second mask being substantially aligned with the first alignment opening formed in the photoresist layer when performing the second step exposure process;
• forming an alignment mark in the first alignment opening;
• and
• forming a plurality of conductive wirings in the first wiring openings and the second wiring openings, wherein the conductive wirings are electrically connected to the at least one integrated circuit component.