Integration scheme for breakdown voltage enhancement of a piezoelectric metal-insulator-metal device

A metal-insulator-metal (MIM) device, comprising:

• a semiconductor substrate;
• a bottom electrode overlying the semiconductor substrate;
• a top electrode overlying the bottom electrode;
• a passivation layer overlying the top electrode;
• a piezoelectric structure between the top electrode and the bottom electrode, wherein the piezoelectric structure comprises a first outer sidewall facing a first direction and a second outer sidewall facing the first direction, wherein the first outer sidewall is laterally offset from the second outer sidewall by a ledge of the piezoelectric structure extending from the first outer sidewall to the second outer sidewall, and wherein the ledge of the piezoelectric structure is in direct contact with the passivation layer;
• and
• wherein the passivation layer comprises an inner sidewall that directly contacts an outer sidewall of the top electrode and the first outer sidewall of the piezoelectric structure, wherein the inner sidewall of the passivation layer is slanted relative to a top surface of the semiconductor substrate, wherein a thickness of the passivation layer directly overlying the ledge of the piezoelectric structure continuously decreases from the first outer sidewall to a first point laterally offset from the first outer sidewall by a non-zero distance in the first direction.

A method for forming a metal-insulator-metal (MIM) structure, comprising:

• forming a bottom electrode over a substrate;
• forming a piezoelectric layer over the bottom electrode, wherein the piezoelectric layer comprises a top region overlying a bottom region;
• forming a top electrode over the piezoelectric layer;
• performing a first patterning process on the top electrode and the top region of the piezoelectric layer according to a first masking layer, wherein the first patterning process defines a first outer sidewall of the piezoelectric layer facing a first direction and an outer sidewall of the top electrode facing the first direction;
• performing a second patterning process on the bottom region of the piezoelectric layer according to a second masking layer, wherein a size of the second masking layer is greater than a size of the first masking layer, wherein the second patterning process defines a second outer sidewall of the piezoelectric layer facing the first direction, wherein the first outer sidewall is laterally offset from the second outer sidewall by a ledge of the piezoelectric layer extending from the first outer sidewall to the second outer sidewall;
• performing a third patterning process on the bottom electrode according to a third masking layer, wherein a size of the third masking layer is greater than the size of the second masking layer;
• and
• forming a passivation layer over the top electrode, the piezoelectric layer, and the bottom electrode, wherein the passivation layer directly contacts the ledge of the piezoelectric layer, wherein the passivation layer comprises an inner sidewall that directly contacts the outer sidewall of the top electrode and the first outer sidewall of the piezoelectric layer, wherein the inner sidewall of the passivation layer is slanted relative to a top surface of the substrate, wherein a thickness of the passivation layer directly overlying the ledge of the piezoelectric layer continuously decreases from the first outer sidewall of the piezoelectric layer to a first point laterally offset from the first outer sidewall by a non-zero distance in the first direction.