Semiconductor memory device including non-volatile storage circuit and operating method thereof

A non-volatile storage device comprising:

• a non-volatile storage circuit including a plurality of fuse sets suitable for sequentially outputting fuse data according to a counting address, each fuse set including an enable fuse, a plurality of address fuses, and a duplication fuse;
• a duplication analysis circuit suitable for storing the counting address corresponding to a duplicated fuse set as a duplication address and activating a duplication enable signal when a repair address inputted from outside is identical to data of the address fuses within the duplicated fuse set;
• an availability analysis circuit suitable for searching an available fuse set according to data of the enable fuse, storing the counting address corresponding to the available fuse set as an available address, and activating an availability enable signal;
• a program enable circuit suitable for outputting, as a program enable signal, the duplication enable signal or the availability enable signal according to a program mode signal;
• and
• an address selection circuit suitable for outputting, as a fuse address, the duplication address or the available address according to the program mode signal.

A semiconductor memory device comprising:

• a memory array area including normal memory cells and redundant memory cells which replace defective memory cells among the normal memory cells;
• a non-volatile storage circuit including a plurality of fuse sets suitable for programming a repair address of the defective memory cells, and sequentially outputting fuse data according to a counting address, each fuse set including an enable fuse, a plurality of address fuses and a duplication fuse;
• a read control circuit suitable for receiving the fuse data, and outputting latch data by selectively masking data of the enable fuse and the address fuses using data of the duplication fuse within the received fuse data;
• and
• a latch circuit including a plurality of latches suitable for storing the latch data in response to a plurality of storing signals which are sequentially activated.

A method of operating a semiconductor memory device including a non-volatile storage circuit having a plurality of fuse sets each including an enable fuse, a plurality of address fuses, and a duplication fuse, the method comprising:

• sequentially outputting fuse data from the fuse sets according to a counting address;
• storing the counting address corresponding to a duplicated fuse set among the fuse sets as a duplication address and activating a duplication enable signal when a repair address is identical to data of the address fuses within the duplicated fuse set;
• searching an available fuse set among the fuse sets according to data of the enable fuse, storing the counting address corresponding to the available fuse set as an available address, activating an availability enable signal;
• and
• programming the duplication fuse of the duplicated fuse set corresponding to the duplication address according to the duplication enable signal when a program mode signal is a first logic level, or programming the repair address into the available fuse set corresponding to the available address according to the availability enable signal when the program mode signal is a second logic level.

A method of operating a semiconductor memory device including a non-volatile storage circuit having a plurality of fuse sets each including an enable fuse, a plurality of address fuses, and a duplication fuse, the method comprising:

• sequentially outputting fuse data from the fuse sets according to a counting address;
• outputting latch data by selectively masking data of the enable fuse and the address fuses using data of the duplication fuse among the fuse data;
• and
• storing the latch data into a plurality of latches in response to a plurality of storing signals which are sequentially activated.