Semiconductor memory device

A semiconductor memory device comprising:

• a memory cell array including a plurality of memory cells;
• a word line connected to gates of the plurality of memory cells;
• a word line driver configured to apply a program voltage to the word line during a program operation of a write operation to write data into the plurality of memory cells, and to apply a verify voltage to the word line during a verify operation of the write operation;
• a plurality of bit lines connected to the plurality of memory cells, respectively;
• a sense amplifier circuit configured to apply a bit line voltage to the plurality of bit lines during the program operation and to detect the data written into the plurality of memory cells via the plurality of bit lines during the verify operation;
• and
• a control circuit configured to control the word line driver and the sense amplifier circuit to execute the write operation in a plurality of loops executed in sequence, the program voltage being increased for each subsequent loop of the write operation, wherein
• when writing data into a target memory cell connected to the word line, the control circuit executes at least first and second loops in the sequence, and
• in executing the first loop, the control circuit applies a first program voltage to the word line during the program operation to increase a threshold voltage of the target memory cell to a target threshold voltage range, and applies a verify voltage corresponding to the data to the word line during the verify operation, and
• upon detecting that the verify operation in the first loop neither passed nor failed, the control circuit selects one of at least two pass write voltages to be applied to the bit line connected to the target memory cell during the program operation of the second loop according to the target threshold voltage range.

A semiconductor memory device comprising:

• a memory cell array including a plurality of memory cells;
• a word line connected to gates of the plurality of memory cells;
• a word line driver configured to apply a program voltage to the word line during a program operation of a write operation to write data into the plurality of memory cells, and to apply a verify voltage to the word line during a verify operation of the write operation;
• a plurality of bit lines connected to the plurality of memory cells, respectively;
• a sense amplifier circuit configured to apply a bit line voltage to the plurality of bit lines during the program operation and to detect the data written into the plurality of memory cells via the plurality of bit lines during the verify operation;
• and
• a control circuit configured to control the word line driver and the sense amplifier circuit to execute the write operation in a plurality of loops executed in sequence, the program voltage being increased for each subsequent loop of the write operation, wherein
• when writing data into a target memory cell connected to the word line, the control circuit executes at least first and second loops in the sequence, and
• in executing the first loop, the control circuit applies a first program voltage to the word line during the program operation to increase a threshold voltage of the target memory cell to a target threshold voltage range, and applies a verify voltage corresponding to the data to the word line during the verify operation, and
• upon detecting that the verify operation in the first loop neither passed nor failed, the control circuit selects one of at least two pass write voltages to be applied to the bit line connected to the target memory cell during the program operation of the second loop according to a second program voltage to be applied during the word line during the program operation of the second loop.