Memory device and method of operating the memory device
AssigneeSK hynix Inc.
InventorsYoung Don Jung, Jung Mi Ko, Kwang Ho Baek, Chang Han Son, Jung Hwan Lee
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Abstract
The present technology relates to a memory device and method of operating the memory device. The memory device includes a plurality of memory cells, a peripheral circuit, and control logic. The peripheral circuit performs a plurality of program loops each including a program operation and a verify operation on selected memory cells of the plurality of memory cells. The control logic controls the peripheral circuit to increase a potential of selected bit lines.
Claims33
A memory device comprising:
- a plurality of memory cells;
- a peripheral circuit configured to perform a plurality of program loops each including a program operation and a verify operation on selected memory cells of the plurality of memory cells;
- and
- control logic configured to control the peripheral circuit to increase a potential of selected bit lines among bit lines connected to the selected memory cells to a reference voltage level during a first period and increase the potential of the selected bit lines to a final voltage level during a second period, in the program operation,
- the reference voltage level is determined differently according to a program loop count indicating the number of program loops that have been successively performed.
A memory device comprising:
- a plurality of memory cells;
- a peripheral circuit configured to perform a plurality of program loops each including a program operation and a verify operation on selected memory cells of the plurality of memory cells;
- and
- control logic configured to control the peripheral circuit to increase a potential of the bit lines connected to the selected memory cells to a target voltage level, in the verify operation,
- wherein the target voltage level is determined differently according to a program loop count indicating the number of program loops that have been successively performed.
A method of operating a memory device that performs a plurality of program loops each including a program step and a verify step for selected memory cells of a plurality of memory cells,
- wherein the program step comprises:
- increasing a potential of selected bit lines among bit lines connected to the selected memory cells to a reference voltage level;
- and
- increasing the potential of the selected bit lines from the reference voltage level to a final voltage level, and
- wherein the reference voltage level is determined differently according to a program loop count indicating the number of program loops that have been successively performed.
A method of operating a memory device that performs a plurality of program loops each including a program step and a verify step for selected memory cells of a plurality of memory cells,
- wherein the verify step comprises:
- applying a verify voltage to a word line connected to the selected memory cells;
- and
- increasing a potential of bit lines connected to the selected memory cells to a target voltage level, and
- wherein the target voltage level is determined differently according to a program loop count indicating the number of program loops that have been successively performed.
Dependencies are inferred from the claim text.