Program disturb improvements in multi-tier memory devices including improved non-data conductive gate implementation

A method, comprising:

• at an apparatus comprising:
• a NAND string extending in a lower tier and an upper tier of a stack, the lower tier comprising a first plurality of memory cells and the upper tier comprising a second plurality of memory cells, wherein each memory cell of the first and second pluralities of memory cells is connected to a respective word line;
• a joint region formed of a dielectric material and disposed between the lower tier and the upper tier of the stack;
• a first non-data memory cell adjacent to and below the joint region;
• a second non-data memory cell adjacent to and above the joint region;
• and
• a conductive gate connected to the first non-data memory cell and the second non-data memory cell;
• wherein the conductive gate forms a joint word line in electrical contact with a gate of the first non-data memory cell and a gate of the second non-data memory cell:
• subsequent to a program verify phase of a program function, performing a first voltage ramp-down operation on the joint word line;
• and
• after a delay of a non-zero time period with respect to the performing of the first voltage ramp-down operation, performing a second voltage ramp-down operation on one or more non-joint word lines connected to one or more respective memory cells of the second plurality of memory cells.

An apparatus, comprising:

• a NAND string extending along a lower tier and an upper tier of a stack, the lower tier comprising a first plurality of memory cells and the upper tier comprising a second plurality of memory cells, wherein each memory cell of the first and second pluralities of memory cells is connected to a respective word line;
• a joint region formed of a dielectric material and disposed between the lower tier and the upper tier of the stack;
• a first non-data memory cell adjacent to and below the joint region;
• a second non-data memory cell adjacent to and above the joint region;
• a conductive gate extending through the joint region and connecting to the first non-data memory cell and the second non-data memory cell, wherein the conductive gate forms a joint word line in electrical contact with a gate of the first non-data memory cell and a gate of the second non-data memory cell;
• means for performing, subsequent to a program verify phase of a program function, a first voltage ramp-down operation on the joint word line;
• and
• means for performing, after a delay of a non-zero time period with respect to the performing of the first voltage ramp-down operation, a second voltage ramp-down operation on one or more non-joint word lines connected to one or more respective memory cells of the second plurality of memory cells.