Semiconductor device and its power supply control method

A semiconductor device comprising:

• a semiconductor chip including:
• a first nonvolatile memory having a first memory block and a second memory block on a side A of the first nonvolatile memory, and a third memory block and a fourth memory block on a side B of the first nonvolatile memory;
• a Central Processing Unit (CPU) electrically connected to the first nonvolatile memory;
• a first switch electrically connected to the first memory block and controlling a supply of a first power supply voltage to the first memory block;
• a second switch electrically connected to the second memory block and controlling the supply of the first power supply voltage to the second memory block;
• a third switch electrically connected to the third memory block and controlling the supply of the first power supply voltage to the third memory block;
• a fourth switch electrically connected to the fourth memory block and controlling the supply of the first power supply voltage to the fourth memory block;
• a second nonvolatile memory electrically connected to each of the first switch, the second switch, the third switch, and the fourth switch, and in which flag information for controlling the first switch, the second switch, the third switch, and the fourth switch is stored;
• and
• a plurality of discrimination circuits discriminating the side A or the side B and electrically connected to each of the first switch, the second switch, the third switch, and the fourth switch,
• wherein the discrimination circuits discriminate whether or not program data to be executed by the CPU is written to the side A and the side B based on the flag information, and
• wherein the control of the first switch, the second switch, the third switch, and the fourth switch is executed based on a discrimination result of the discrimination circuit.

A power supply control method of a semiconductor device comprising of:

• (a) reading a boot program stored in a Read Only Memory (ROW by a Central Processing Unit (CPU);
• (b) after the step (a), reading, by the CPU, flag information for controlling 1) a first switch electrically connected to a first memory block of a first nonvolatile memory and 2) a second switch electrically connected to a second memory block of the first nonvolatile memory, wherein the flag information is read from a second nonvolatile memory;
• and
• (c) after the step (b), controlling the first switch and the second switch based on the flag information, whereby the CPU controls a supply of a first power supply voltage to the first memory block and the supply of the first power supply voltage to the second memory block,
• wherein the flag information is information indicating whether program data to be executed by the CPU has been written to the first memory block and the second memory block.