Memory device and method of reading data

A non-volatile memory, comprising:

• a memory cell region including a first metal pad;
• a peripheral circuit region including a second metal pad and vertically connected to the memory cell region by the first metal pad and the second metal pad;
• a memory cell array region in the memory cell region including a first end, an outer region proximate the first end and an inner region separated from the first end by the outer region;
• first and second bit lines in the memory cell region;
• an outer memory cell string in the memory cell region including memory cells connected to an outer pillar extending vertically upward through the outer region, and an inner memory cell string including memory cells connected to an inner pillar extending vertically upward through the inner region;
• and
• a data input/output (I/O) circuit in the peripheral circuit region including:
• a page buffer circuit including a first page buffer that connects the first bit line during a first read operation directed to memory cells of the outer memory cell string, and a second page buffer that connects the second bit line during a second read operation directed to memory cells of the inner memory cell string, and
• a read voltage determination unit that selects a first optimal read voltage used during the first read operation, and a second optimal read voltage, different from the first optimal read voltage, used during the second read operation,
• wherein the first page buffer includes a first storing register that stores a first candidate read voltage and a second storing register that store a second candidate read voltage, and
• the read voltage determination unit selects one of the first candidate read voltage and the second candidate read voltage as the first optimal read voltage.

A vertical NAND flash memory, comprising:

• a memory cell region including a first metal pad;
• a peripheral circuit region including a second metal pad and vertically connected to the memory cell region by the first metal pad and the second metal pad;
• a NAND memory cell array region bounded on a first end by a first word line cut and bounded on a second end opposite the first end by a second word line cut, wherein the NAND memory cell array region is in the memory cell region and includes a first outer region proximate the first end, a second outer region proximate the second end, and an inner region between the first outer region and the second outer region;
• bit lines in the memory cell region that extend over the NAND memory cell array region and include a first bit line and a second bit line;
• a first outer NAND string in the memory cell region including NAND cells connected to an outer pillar extending vertically upward through the first outer region, and a second outer NAND string including NAND cells connected to an outer pillar extending vertically upward through the second outer region;
• a first inner NAND string in the memory cell region including NAND cells connected to a first inner pillar extending vertically upward through the inner region, and a second inner NAND string including NAND cells connected to a second inner pillar extending vertically upward through the inner region;
• and
• a data input/output (I/O) circuit in the peripheral circuit region including:
• a page buffer circuit including a first page buffer that connects the first bit line during a first read operation directed to memory cells of at least one of the first outer NAND string and the second outer NAND string, and a second page buffer that connects the second bit line during a second read operation directed to memory cells of at least one of the first inner NAND string and the second inner NAND string, and
• a read voltage determination unit that selects a first optimal read voltage used during the first read operation, and a second optimal read voltage used during the second read operation.