Apparatus for determining data states of memory cells

A memory, comprising:

• an array of memory cells comprising a plurality of memory cells;
• and
• a controller for access the array of memory cells, wherein the controller is configured to cause the memory to:
• generate a plurality of stepped voltage levels, wherein each voltage level of the plurality of stepped voltage levels has a respective predetermined value;
• apply the plurality of stepped voltage levels to an access line connected to a respective control gate of each memory cell of the plurality of memory cells;
• determine a respective activation voltage level for each memory cell of the plurality of memory cells, wherein the respective activation voltage level for each memory cell of the plurality of memory cells corresponds to a minimum voltage level of the plurality of stepped voltage levels that is determined to cause that memory cell to activate in response to applying the plurality of stepped voltage levels to the access line;
• determine a plurality of activation voltage level distributions based on the respective activation voltage levels for each memory cell of a plurality of first subsets of memory cells of the plurality of memory cells, wherein each activation voltage level distribution of the plurality of activation voltage level distributions comprises the respective activation voltage level of each memory cell of a respective first subset of memory cells of the plurality of first subsets of memory cells;
• determine a plurality of transition voltage levels based on the plurality of activation voltage level distributions, wherein each transition voltage level of the plurality of transition voltage levels corresponds to one of the plurality of stepped voltage levels and represents a respective transition identified between a respective adjacent pair of activation voltage level distributions of the plurality of activation voltage level distributions;
• and
• assign a respective data state of a plurality of data states to each memory cell of a second subset of memory cells of the plurality of memory cells based on the determined activation voltage level of that memory cell and the determined plurality of transition voltage levels.

A memory, comprising:

• an array of memory cells comprising a plurality of memory cells;
• an access line connected to a control gate of each memory cell of the plurality of memory cells;
• a counter configured to generate a plurality of count values in a sequence, wherein each count value of the plurality of count values is greater than any preceding count value of the plurality of count values, and less than any subsequent count value of the plurality of count values, in the sequence;
• a digital-to-analog converter (DAC) having an input configured to receive the plurality of count values and having an output selectively connected to the access line, wherein the DAC is configured to generate a respective predetermined voltage level of a plurality of predetermined voltage levels at its output for each count value of the plurality of count values;
• and
• a controller for access the array of memory cells, wherein the controller is configured to cause the memory to:
• connect the access line to the output of the DAC;
• generate the plurality of count values in the sequence;
• generate the plurality of voltage levels in response to the plurality of count values, thereby applying the plurality of voltage levels to the access line;
• determine a plurality of activation voltage levels for the plurality of memory cells, wherein each activation voltage level of the plurality of activation voltage levels corresponds to a minimum voltage level of the plurality of voltage levels that is determined to cause a respective memory cell of the plurality of memory cells to activate in response to applying that activation voltage level to the access line;
• determine a plurality of activation voltage level distributions based on a subset of the plurality of activation voltage levels, wherein each activation voltage level distribution of the plurality of activation voltage level distributions corresponds to a respective first subset of memory cells of a plurality of first subsets of memory cells of the plurality of memory cells, and wherein a number of activation voltage level distributions of the plurality of activation voltage level distributions is an integer value D;
• determine a plurality of transition voltage levels based on the plurality of activation voltage level distributions, wherein each transition voltage level of the plurality of transition voltage levels corresponds to one of the plurality of voltage levels and represents a respective transition identified between a respective adjacent pair of activation voltage level distributions of the plurality of activation voltage level distributions;
• assign a first data state of a plurality of data states to each memory cell of a second subset of memory cells of the plurality of memory cells that has a respective activation voltage level that is less than a lowest transition voltage level of the plurality of transition voltage levels, wherein each data state of the plurality of data states corresponds to a respective activation voltage level distribution of the plurality of activation voltage level distributions;
• assign a highest data state of the plurality of data states to each memory cell of the second subset of memory cells of the plurality of memory cells that has a respective activation voltage level that is greater than a highest transition voltage level of the plurality of transition voltage levels;
• and
• for each integer value of N, wherein 2<=N<=(D−1), assign an Nth data state of the plurality of data states to each memory cell of the second subset of memory cells of the plurality of memory cells that has a respective activation voltage level that is greater than an (N−1)th transition voltage level of the plurality of transition voltage levels and less than an Nth transition voltage level of the plurality of transition voltage levels, wherein each remaining transition voltage level of the plurality of transition voltage levels is either less than the (N−1)th transition voltage level or greater than Nth transition voltage level.