Memory device with adaptive noise and voltage suppression during read-while-write operations

A selection circuit configured to multiplex between shared read and write IO lines and bit lines in a memory array comprising first and second memory banks, the selection circuit comprising:

• a) a first selection device controllable by a first address decoded write enable signal, and coupled between the write IO line and a first node;
• b) a second selection device controllable by a first address decoded read enable signal, and coupled between the read IO line and a second node;
• c) a first suppression device controllable by the first address decoded write enable signal, and coupled between the second node and a ground;
• d) a second suppression device controllable by the first address decoded read enable signal, and coupled between the first node and the ground;
• e) a first selection/isolation device controllable by a second address decoded write enable signal, and coupled between a first bit line and the first node;
• f) a second selection/isolation device controllable by a third address decoded write enable signal, and coupled between a second bit line and the first node;
• g) a third selection/isolation device controllable by a fourth address decoded write enable signal, and coupled between the first bit line and the second node;
• and
• h) a fourth selection/isolation device controllable by a fifth address decoded write enable signal, and coupled between the second bit line and the second node.

A selection circuit configured to multiplex between first and second IO lines, and bit lines in a memory array that simultaneously supports first and second operations, the selection circuit comprising:

• a) a plurality of selection devices configured to control simultaneous paths between the first and second IO lines and the bit lines, wherein the first IO line is allocated for the first operation, and the second IO line is allocated for the second operation;
• b) a plurality of suppression devices configured to suppress noise due to transitions on the first IO line during the second operation, and to suppress noise due to transitions on the second IO line during the first operation;
• and
• c) a plurality of isolation devices configured to isolate noise due to the transitions on the first IO line during the second operation, and to isolate noise due to the transitions on the second IO line during the first operation.