Memory device and control method thereof for fast read
AssigneeWinbond Electronics Corp.
InventorWen-Chiao Ho
Life of this patent
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Abstract
A memory device includes a memory array. The memory array has a plurality of memory cells arranged in rows and columns. The gates of the memory cells in the same row are coupled to each other and connected to a word line. The drains of the memory cells in the same column are coupled to each other and connected to a bit line. The sources of the memory cells in the same row are coupled to each other, and the sources of the memory cells in the two adjacent rows are connected to different respective source lines.
Claims11
A memory device, comprising:
- a memory array, having a plurality of memory cells arranged in rows and columns;
- wherein gates of the memory cells in the same row are coupled to each other and connected to a word line;
- drains of the memory cells in the same column are coupled to each other and connected to a bit line;
- sources of the memory cells in the same row are coupled to each other, and sources of the memory cells in the two adjacent rows are connected to different respective source lines;
- wherein the different source lines comprise a first source line and a second source line;
- and
- a word line controller, when a target memory cell whose source is connected to the first source line needs to be read, the word line controller provides a first voltage to a word line corresponding to the target memory cell and also provides the first voltage to a word line corresponding to the next row of the target memory cell, so that a period when the word line corresponding to the target memory cell remains at the first voltage overlaps a period when the word line corresponding to the next row of the target memory cell remains at the first voltage.
A control method of a memory device, wherein the memory device comprises a memory array, the memory array is comprised of a plurality of memory cells arranged in rows and columns;
- the gates of the memory cells in the same row are coupled to each other and connected to a word line;
- the drains of the memory cells in the same column are coupled to each other and connected to a bit line;
- the sources of the memory cells in the same row are coupled to each other, and the sources of the memory cells in the two adjacent rows are connected to different respective source lines;
- a first memory cell is located in a row of the plurality of rows and is located in the last of the plurality of columns;
- a second memory cell is located in a row next to the row where the first memory cell is located and is located in the last column;
- a third memory cell is located in a row next to the row where the second memory cell is located and is located in the last of the plurality of columns;
- a fourth memory cell is located in a row next to the row where the first memory cell is located and is located in the first of the plurality of columns;
- and when the first memory cell is read, the control method comprises:
- providing a first voltage to a word line connected to the first memory cell, providing a second voltage to a source line connected to the first memory cell, and providing a third voltage to a bit line connected to the first memory cell, wherein the third voltage is higher than the second voltage;
- providing the first voltage to a word line connected to the fourth memory cell, providing a fourth voltage to a source line connected to the second memory cell, and providing the second voltage to a source line connected to the third memory cell;
- wherein the fourth voltage is equal to the third voltage;
- stopping the first voltage to the word line connected to the first memory cell;
- wherein a period when the word line connected to the first memory cell remains at the first voltage overlaps a period when the word line connected to the second and fourth memory cell remains at the first voltage.
Dependencies are inferred from the claim text.