Search circuits, hammer address management circuits, and memory systems including the same

A memory system comprising:

• a memory cell array comprising a plurality of memory cells;
• a hammer address management circuit configured to determine a hammer address of the memory cell array that is accessed intensively;
• and
• a refresh controller configured to perform a hammer refresh operation to refresh a first row of the memory cell array that is physically adjacent to a second row of the memory cell array corresponding to the hammer address, wherein the hammer address management circuit comprises:
• an address storage configured to store a plurality of row addresses based on an access address signal;
• a content-addressable memory (CAM) comprising a plurality of CAM cells configured to store a plurality of access count data indicating a plurality of access counts of the plurality of row addresses, each access count data comprising a first bit corresponding to a least significant bit through a K-th bit corresponding to a most significant bit, the CAM configured to provide a plurality of matching signals indicating whether each of the plurality of access count data matches searching data;
• a CAM controller configured to perform a partial searching operation such that the CAM controller applies comparison bits corresponding to a portion of the first through K-th bits as the searching data to the CAM and searches for target count data among the plurality of access count data based on the plurality of matching signals indicating that the corresponding bits of the target count data match the comparison bits;
• and
• an address controller configured to provide the hammer address among the plurality of row addresses stored in the address storage, based on a result of searching for the target count data.

A hammer address management circuit of a memory system, comprising:

• an address storage configured to store a plurality of row addresses based on an access address signal provided to a memory device;
• a content-addressable memory (CAM) comprising a plurality of CAM cells configured to store a plurality of access count data indicating a plurality of access counts of the plurality of the plurality of row addresses, each access count data including a first bit corresponding to a least significant bit through a K-th bit corresponding to a most significant bit, the CAM configured to provide a plurality of matching signals indicating whether each of the plurality of access count data matches searching data;
• a CAM controller configured to perform a partial searching operation such that the CAM controller applies comparison bits corresponding to a portion of the first through K-th bits as the searching data to the CAM and search for target count data among the plurality of access count data based on the plurality of matching signals indicating that the corresponding bits of the target count data match the comparison bits;
• and
• an address controller configured to provide a hammer address of the memory device that is accessed intensively, based on a result of searching for the target count data.