Non-volatile static random access memory (nvSRAM) with multiple magnetic tunnel junction cells
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsPerng-Fei Yuh, Yih Wang, Ku-Feng Lin, Jui-Che Tsai, Hiroki Noguchi, Fu-An Wu
Life of this patent
Estimating the term…
Abstract
Disclosed herein is an integrated circuit including multiple magnetic tunneling junction (MTJ) cells coupled to a static random access memory (SRAM). In one aspect, the integrated circuit includes a SRAM having a first port and a second port, and a set of pass transistors coupled to the first port of the SRAM. In one aspect, the integrated circuit includes a set of MTJ cells, where each of the set of MTJ cells is coupled between a select line and a corresponding one of the set of pass transistors.
Claims15
An integrated circuit comprising:
- a first static random access memory (SRAM) having a first port and a second port;
- a first set of pass transistors;
- a first set of magnetic tunnel junction (MTJ) cells, each of the first set of MTJ cells and a corresponding one of the first set of pass transistors coupled to each other in series between a first select line and the first port of the first SRAM;
- a second SRAM having a third port and a fourth port;
- a second set of pass transistors;
- and
- a second set of MTJ cells and a corresponding one of the second set of pass transistors coupled to each other in series between a second select line and the third port of the second SRAM,
- wherein a first reference MTJ cell of the first set of MTJ cells is coupled to a second reference MTJ cell of the second set of MTJ cells through a first reference line.
A device comprising:
- a first static random access memory (SRAM);
- a second SRAM;
- a first set of magnetic tunnel junction (MTJ) cells coupled to the first SRAM;
- a second set of MTJ cells coupled to the second SRAM;
- and
- a memory controller to:
- write a first bit to one of the first set of MTJ cells through the first SRAM during a first time period,
- write a second bit to one of the second set of MTJ cells through the second SRAM during a second time period, the first time period and the second time period partially overlapping with each other, and
- write a third bit to another one of the first set of MTJ cells through the first SRAM during a third time period after the first time period.
A method comprising:
- applying, to a first port of a first static random access memory (SRAM), a reference resistance;
- applying, to a second port of the first SRAM, a resistance of one of a first set of magnetic tunnel junction (MTJ) cells, the first SRAM to generate a voltage at the first port or the second port of the first SRAM according to a difference between the reference resistance applied to the first port and the resistance of the one of the first set of MTJ cells applied to the second port of the first SRAM;
- and
- determining a bit stored by the one of the first set of MTJ cells according to the voltage, wherein a first reference MTJ cell is coupled to the first SRAM and a second reference MTJ cell is coupled to a second SRAM, wherein the first set of MTJ cells is coupled to the second reference MTJ cell through a reference line, the method further comprising:
- programming the first reference MTJ cell in a first state;
- and
- programming the second reference MTJ cell in a second state.
Dependencies are inferred from the claim text.