Molecular synthesis device
AssigneeImec Vzw
InventorsAntonio Arreghini, Arnaud Furnemont
Life of this patent
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Abstract
The disclosed technology relates to a molecular synthesis device. In one aspect, the molecular synthesis device comprises a synthesis array having an array of synthesis locations and an electrode arranged at each synthesis locations. The molecular synthesis device further comprises a non-volatile memory having an array of bit cells and a set of wordlines and a set of bitlines. Each bit cell comprises a non-volatile memory transistor having a control gate connected to a wordline, a first source/drain terminal, and a second source/drain terminal connected to a bitline. The electrode at each synthesis locations of the synthesis array is connected to the first source/drain terminal of a corresponding bit cell of the non-volatile memory.
Claims22
A molecular synthesis device comprising:
- a synthesis array having:
- an array of synthesis locations;
- and
- an electrode arranged at each synthesis location;
- a non-volatile memory having:
- an array of bit cells;
- a set of wordlines;
- and
- a set of bitlines,
- wherein each bit cell comprises:
- a non-volatile memory transistor having a control gate connected to a wordline;
- a first source/drain terminal;
- and
- a second source/drain terminal connected to a bitline,
- wherein the electrode at each synthesis location of the synthesis array is connected to the first source/drain terminal of a corresponding bit cell of the non-volatile memory, and wherein the memory transistor of each bit cell is switchable between a low threshold voltage and a high threshold voltage;
- and
- a controller configured to:
- receive a data set indicating which electrodes of the synthesis array are to be enabled;
- set the memory transistors of each bit cell, connected to electrodes to be enabled, to the low threshold voltage and set the memory transistors of all other bit cells to the high threshold voltage;
- and
- apply a control voltage, intermediate between the low and the high threshold voltages, to the wordlines and an electrode voltage to the bitlines.
A method of selectively activating electrodes of an array of synthesis locations, wherein the electrode of each synthesis location is connected to a first source/drain terminal of a non-volatile memory transistor of a corresponding bit cell of an array of bit cells of a non-volatile memory device, and wherein the memory transistor of each bit cell is switchable between a low threshold voltage and a high threshold voltage and has a control gate connected to a wordline of a set of wordlines of the non-volatile memory device and a second source/drain terminal connected to a bitline of a set of bitlines of the non-volatile memory device, the method comprising:
- setting the memory transistors of each bit cells, connected to electrodes which are to be enabled, to the low threshold voltage and the memory transistors of all other bit cells to the high threshold voltage;
- and
- applying a control voltage, intermediate between the low and the high threshold voltages, to the wordlines and an electrode voltage to the bitlines.
Dependencies are inferred from the claim text.