US 11,107,522 B2 · Multi-level cell programming using optimized multiphase mapping with balanced gray code

Abstract

Disclosed are systems and methods for providing programming of multi-level memory cells using an optimized multiphase mapping with a balanced Gray code. A method includes programming, in a first phase, a first portion of data into memory cells in a first-level cell mode. The method may also include reading, from the memory cells, the programmed first portion of the data. The method may also include programming, in a second phase, a second portion of the data into the memory cells in a second-level cell mode, wherein programming the second phase is based on applying, to the read first portion of the data, a mapping from the first-level cell mode to the second-level cell mode. The mapping may be selected based on minimizing an average voltage change of the memory cells from the first to second phase while maintaining a balanced Gray code.

Claims20

Dependent claims

A data storage system, comprising:

memory cells;
and
one or more controllers configured to cause:
writing, in a first phase, a first data portion into the memory cells in a first-level cell mode;
and
writing, in a second phase, a second data portion into the memory cells in a second-level cell mode, based on a mapping between the first-level cell mode and the second-level cell mode,
wherein:
a difference between transition counts of any two pages of memory pages in the second-level cell mode does not exceed a transition count difference,
a sum of the transition counts for the memory pages in the second-level cell mode does not exceed a maximum number of programming levels in the second-level cell mode,
a number of transition counts for each page of multiple pages associated with the first phase is different from a number of transition counts for a corresponding page of multiple pages associated with the second phase, and
the transition count difference is an integer.

8 more elements

A method, comprising:

writing, in a first phase, a first data portion into memory cells in a first-level cell mode;
and
writing, in a second phase, a second data portion into the memory cells in a second-level cell mode, based on a mapping between the first-level cell mode and the second-level cell mode,
wherein:
a difference between transition counts of any two pages of memory pages in the second-level cell mode does not exceed a transition count difference,
a sum of the transition counts for the memory pages in the second-level cell mode does not exceed a maximum number of programming levels in the second-level cell mode,
a number of transition counts for each page of multiple pages associated with the first phase is different from a number of transition counts for a corresponding page of multiple pages associated with the second phase, and
the transition count difference is an integer.

5 more elements

An apparatus, comprising:

means for writing, in a first phase, a first data portion into memory cells in a first-level cell mode;
and
means for writing, in a second phase, a second data portion into the memory cells in a second-level cell mode, based on a mapping between the first-level cell mode and the second-level cell mode,
wherein:
a difference between transition counts of any two pages of memory pages in the second-level cell mode does not exceed a transition count difference,
a sum of the transition counts for the memory pages in the second-level cell mode does not exceed a maximum number of programming levels in the second-level cell mode,
a number of transition counts for each page of multiple pages associated with the first phase is different from a number of transition counts for a corresponding page of multiple pages associated with the second phase, and
the transition count difference is an integer.

5 more elements

Dependencies are inferred from the claim text.

Multi-level cell programming using optimized multiphase mapping with balanced gray code

Life of this patent

Multi-level cell programming using optimized multiphase mapping with balanced gray code

Life of this patent

Abstract

Claims20