Semiconductor memory device with cache latches
AssigneeSK hynix Inc.
InventorsSung Lae Oh, Dong Hyuk Kim, Tae Sung Park, Soo Nam Jung
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Abstract
A semiconductor memory device may include a memory cell array; and a cache latch circuit that exchanges data with the memory cell array through a plurality of bit lines extended in a second direction crossing a first direction. The memory cell array may include a plurality of cache latches arranged in a plurality of columns in the first direction and in a plurality of rows in the second direction. Each of the cache latches may be coupled to any one of a plurality of input/output (IO) pins. Cache latches coupled to the IO pins at the same time may constitute one IO cache latch unit. The cache latches included in the one IO cache latch unit may be arranged in 2×2 array units.
Claims20
A semiconductor memory device comprising:
- a memory cell array;
- a cache latch circuit configured to exchange data with the memory cell array through a plurality of bit lines extending in a second direction crossing a first direction;
- a plurality of even bit lines and a plurality of odd bit lines;
- and
- a plurality of input/output (IO) pins,
- wherein the cache latch circuit comprises a plurality of cache latches arranged in a plurality of columns that are arranged in the first direction and in a plurality of rows that are arranged in the second direction,
- wherein the cache latches in two adjacent columns are divided into a plurality of sections, arranged in the second direction, that are separated by a bit line select transistor and a sensing latch,
- wherein the cache latches in each section comprise a plurality of rows of even cache latches coupled to even bit lines and a plurality of rows of odd cache latches coupled to odd bit lines,
- wherein even cache latches in two adjacent columns or odd cache latches in two adjacent columns that are simultaneously selected to output data in parallel to the plurality of IO pins comprise one IO cache latch unit,
- and
- wherein the selected cache latches in the one IO cache latch unit are arranged in 2×2 array units in each of the plurality of sections.
A semiconductor memory device comprising:
- a memory cell array;
- a plurality of bit lines extending in a second direction crossing a first direction, and comprising a plurality of even bit lines and a plurality of odd bit lines that are alternately arranged in the first direction;
- and
- a cache latch circuit, configured to exchange data with the memory cell array through the plurality of bit lines, comprising a plurality of cache latches arranged in a plurality of columns in the first direction and in a plurality of rows in the second direction,
- wherein the plurality of rows are divided into a plurality of sections by a plurality of sensing latches,
- wherein the plurality of cache latches are coupled to any one of a 2N IO pins (where N is a positive integer),
- wherein a 2N cache latches coupled to even bit lines and simultaneously selected to output data in parallel to the 2N IO pins comprise a first IO cache latch unit,
- wherein a 2N cache latches coupled to odd bit lines and simultaneously selected to output data in parallel to the 2N IO pins comprise a second IO cache latch unit,
- wherein a cache latch unit comprises the first IO cache latch unit and the second IO cache latch unit, and
- wherein the cache latches included in each of the first and second IO cache latch units in adjacent columns within a respective section are arranged in 2×2 array units.
A semiconductor memory device comprising:
- a plurality of cache latches arranged in a plurality of sections arranged in a second direction crossing a first direction, and configured to form a plurality of columns and a plurality of rows arranged in the first and second directions, respectively;
- a plurality of sensing latches coupled respectively to the plurality of cache latches, and arranged in the second direction in a plurality of regions located on both sides of each of the plurality of sections;
- and
- a plurality of bit line select transistors arranged in the plurality of regions and coupled between the plurality of sensing latches and a plurality of bit lines extending in the second direction,
- wherein each of the cache latches is coupled to any one of a plurality of IO pins,
- wherein cache latches simultaneously selected to output data in parallel to the plurality of IO pins comprise an IO cache latch unit, and
- wherein the cache latches included in the IO cache latch unit in adjacent columns within a respective section comprise a 2×2 array.
Dependencies are inferred from the claim text.