US 11,107,519 B2 · Techniques for accessing an array of memory cells to reduce parasitic coupling

Abstract

Techniques are described herein for mitigating parasitic signals induced by state transitions during an access operation of a selected memory cell in a memory device. Some memory devices may include a plate that is coupled with memory cells associated with a plurality of digit lines and/or a plurality of word lines. Because the plate is coupled with a plurality of digit lines and/or word lines, unintended coupling between various components of the memory device may occur during an access operation. To mitigate parasitic signals induced by the unintended coupling, the memory device may isolate the selected memory cell from a selected digit line during certain portions of the access operation. The memory device may isolate the selected memory cell when the plate transitions from a first voltage to a second, when the selected digit line transitions from a third voltage to a fourth voltage, or a combination thereof.

Claims20

Dependent claims

A method, comprising:

identifying a digit line transition of a digit line from a first voltage to a second voltage;
isolating a memory cell from the digit line to decouple the digit line from a plate based at least in part on identifying the digit line transition;
biasing the digit line from the first voltage to the second voltage while the memory cell is isolated from the digit line to mitigate a parasitic signal induced on an unselected memory cell;
and
coupling the memory cell with the digit line after the digit line is biased to the second voltage.

2 more elements

A method, comprising:

identifying a digit line transition of a digit line from a first voltage to a second voltage;
isolating a memory cell from the digit line based at least in part on identifying the digit line transition;
biasing the digit line from the first voltage to the second voltage while the memory cell is isolated from the digit line;
coupling the memory cell with the digit line after the digit line is biased to the second voltage;
writing a first logic value to the memory cell based at least in part on biasing the digit line from the first voltage to the second voltage, wherein coupling the memory cell with the digit line after the digit line is biased to the second voltage is based at least in part on writing the first logic value;
identifying a second digit line transition back from the second voltage to the first voltage, the second digit line transition occurring after a write-back operation is complete;
isolating the memory cell from the digit line based at least in part on identifying the second digit line transition;
biasing the digit line from the second voltage to the first voltage while the memory cell is isolated from the digit line;
and
coupling the memory cell with the digit line based at least in part on the digit line being biased to the first voltage.

7 more elements

Dependencies are inferred from the claim text.

Techniques for accessing an array of memory cells to reduce parasitic coupling

Life of this patent

Techniques for accessing an array of memory cells to reduce parasitic coupling

Life of this patent

Abstract

Claims20