Semiconductor memory device and method for refreshing memory with refresh counter

A memory system comprising:

• a memory controller suitable for providing a refresh command with mode signals;
• and
• a memory device suitable for generating a row active signal according to the refresh command and the mode signals, and performing a refresh operation on at least one word line corresponding to a refresh address in response to the row active signal,
• wherein the memory device includes:
• a refresh control circuit suitable for controlling, in response to the refresh command, an activation timing of the row active signal according to the mode signals and a counting signal;
• a refresh counter suitable for generating the counting signal by counting the number of times the row active signal is activated, and generating sequence signals which are sequentially activated;
• and
• a detection circuit suitable for generating flag signals by combining the sequence signals, and generating the detection signal according to a corresponding one of the flag signals when any of the mode signals is activated,
• wherein the refresh counter is initialized by the detection signal.