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US 11,107,515 B2Granted
Ferroelectric memory cells
AssigneeMicron Technology, Inc.
InventorsScott J. Derner, Christopher J. Kawamura
Life of this patent
Estimating the term…
Abstract
Apparatuses and methods are disclosed that include ferroelectric memory cells. An example ferroelectric memory cell includes two transistors and two capacitors. Another example ferroelectric memory cell includes three transistors and two capacitors. Another example ferroelectric memory cell includes four transistors and two capacitors.
Claims24
An apparatus, comprising:
- a first memory cell;
- and
- a second memory cell;
- wherein each memory cell comprises:
- a first transistor;
- a first ferroelectric capacitor including a ferroelectric material, coupled to the first transistor and vertically stacked relative to the first transistor;
- a second transistor;
- a second ferroelectric capacitor coupled to the second transistor and vertically stacked relative to the second transistor;
- and
- a third transistor coupled to the first and second ferroelectric capacitors;
- and
- a plate line structure shared by the first and second memory cells, the plate line structure coupled to the respective third transistor of the first and second memory cells.
9 more elements
An apparatus, comprising:
- a first transistor;
- a first ferroelectric capacitor including a ferroelectric material, coupled to the first transistor and vertically stacked relative to the first transistor;
- a second transistor;
- a second ferroelectric capacitor coupled to the second transistor and vertically stacked relative to the second transistor;
- a third transistor coupled to the first ferroelectric capacitor;
- and
- a fourth transistor coupled to the second ferroelectric capacitor;
- and
- a plate line structure coupled to the respective third and fourth transistors.
6 more elements
An apparatus, comprising:
- a first capacitor including a first plate, a second plate, and a ferroelectric material disposed between the first and second plates, the first plate coupled to a first source/drain region of a third transistor;
- a second capacitor including a first plate, a second plate, and a ferroelectric material disposed between the first and second plates, the first plate coupled to a first source/drain region of a fourth transistor;
- a first transistor vertically displaced relative to the first capacitor and coupled to the second plate of the first capacitor;
- and
- a second transistor vertically displaced relative to the second capacitor and coupled to the second plate of the second capacitor;
- and
- a shared digit line coupled to a first source/drain region of the first transistor and a first source/drain region of the second transistor, wherein the second plate of the first capacitor is coupled to a second source/drain region of the first transistor, and wherein the second plate of the second capacitor is coupled to a second source/drain region of the second transistor.
4 more elements
Dependencies are inferred from the claim text.