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US 11,107,512 B2Granted
Memory device and memory system including the same
AssigneeSamsung Electronics Co., Ltd.
InventorsByunghoon Jeong, Kyungtae Kang, Jangwoo Lee, Jeongdon Ihm
Life of this patent
Estimating the term…
Abstract
A memory device includes a memory cell array configured to store data; and a data output circuit configured to transmit status data to an external device through at least one data line in a latency period in response to a read enable signal received from the external device and transmit the data read from the memory cell array to the external device through the at least one data line in a period subsequent to the latency period.
Claims20
A memory device, comprising:
- a memory cell array configured to store data;
- and
- a data output circuit configured to,
- transmit status data to an external device through at least one data line during a latency period in response to a read enable signal received from the external device, and
- transmit the data stored in the memory cell array to the external device through the at least one data line during a period subsequent to the latency period.
2 more elements
A memory system comprising:
- a memory controller;
- and
- a memory device configured to,
- transmit status data to the memory controller through a plurality of data lines during a latency period in response to a read enable signal received from the memory controller, and
- transmit data stored in the memory device to the memory controller through the plurality of data lines during a period subsequent to the latency period.
2 more elements
A memory device comprising:
- a memory cell array configured to store first data and second data;
- and
- a data output circuit configured to,
- transmit the first data to an external device at a first transmission rate through a plurality of data lines during a latency period in response to a read enable signal received from the external device, and
- transmit the second data to the external device at a second transmission rate through the plurality of data lines in a period subsequent to the latency period.
2 more elements
Dependencies are inferred from the claim text.