Semiconductor memory device
AssigneeToshiba Memory Corporation
InventorsKeiji Hosotani, Fumitaka Arai, Keisuke Nakatsuka
Life of this patent
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Abstract
According to one embodiment, a semiconductor memory device includes: a conductive layer including a first portion and a second portion electrically coupled to the first portion; a first contact plug electrically coupled to the first portion; a first semiconductor layer; a first insulating layer between the second portion and the first semiconductor layer, and between the first portion and the first semiconductor layer; a second contact plug coupled to the first semiconductor layer in a region in which the first insulating layer is formed; a first interconnect; and a first memory cell apart from the second portion in the second direction and storing information between the first semiconductor layer and the first interconnect.
Claims19
A semiconductor memory device comprising:
- a conductive layer including a first portion and a second portion, the first portion extending in a first direction, and the second portion electrically coupled to the first portion and extending in a second direction intersecting the first direction;
- a first contact plug extending in a third direction intersecting the first and second directions, and electrically coupled to the first portion;
- a first semiconductor layer extending in the second direction;
- a first insulating layer between the second portion and the first semiconductor layer, and between the first portion and the first semiconductor layer;
- a second contact plug extending in the third direction, and coupled to the first semiconductor layer in a region in which the first insulating layer is formed;
- a first interconnect extending in the third direction;
- and a first memory cell apart from the second portion in the second direction and storing information between the first semiconductor layer and the first interconnect;
- a second semiconductor layer adjacent to the first semiconductor layer in the first direction and extending in the second direction;
- a fourth insulating layer;
- and a second memory cell apart from the first memory cell in the first direction and storing information between the first interconnect and the second semiconductor layer,
- wherein the conductive layer further includes a third portion apart from the second portion in the first direction and extending in the second direction, and
- the fourth insulating layer is provided between the second semiconductor layer and the third portion, and between the second semiconductor layer and the first portion.
A semiconductor memory device comprising:
- a first semiconductor layer extending in a first direction parallel to a semiconductor substrate;
- a second semiconductor layer above the first semiconductor layer in a second direction perpendicular to the semiconductor substrate, and extending in the first direction;
- third and fourth semiconductor layers respectively arranged adjacent to the first and second semiconductor layers in a third direction intersecting the first and second directions, and extending in the first direction;
- a first interconnect between the first semiconductor layer and the third semiconductor layer, between the second semiconductor layer and the fourth semiconductor layer, and extending in the second direction;
- a first memory cell storing information between the first semiconductor layer and the first interconnect;
- a second memory cell storing information between the second semiconductor layer and the first interconnect;
- a third memory cell storing information between the third semiconductor layer and the first interconnect;
- a fourth memory cell storing information between the fourth semiconductor layer and the first interconnect;
- first to fourth insulating layers that are respectively in contact with sides of the first to fourth semiconductor layers in a first region;
- a first conductive layer including a side that is in contact with the first and third insulating layers in the first region;
- and
- a second conductive layer above the first conductive layer and including a side that is in contact with the second and fourth insulating layers in the first region.
Dependencies are inferred from the claim text.