US 11,107,507 B2 · Transmitting data signals on separate layers of a memory module, and related methods, systems and apparatuses

Abstract

Systems, apparatuses, and methods for routing and transmitting signals in an electronic device are described. Various signal paths may be routed to avoid or limit reference transitions or transitions between layers of a structure of a device (e.g., printed circuit board (PCB)). In a memory module, for example, different data inputs/outputs (e.g., DQs) may be routed through different layers of a PCB according to their relative location to one another. For instance, DQs associated with even bits of a byte may be routed on one layer of a PCB near one ground plane, and DQs associated with odd bits of the byte may be routed on a different layer of the PCB near another ground plane. Each of the DQs may be subject to a single reference layer change, which may occur at or near a DRAM of a memory module (e.g., in the DRAM ball grid array (BGA) area).

Claims20

Dependent claims

A method comprising:

transmitting a first set of data signals associated with a memory access operation on a first signal layer of a printed circuit board (PCB) of a dual-rank dual in-line memory module (DIMM) to or from a first memory device of the dual-rank DIMM;
and
transmitting a second set of data signals associated with the memory access operation on a second signal layer of the PCB of the dual-rank DIMM to or from the first memory device of the dual-rank DIMM, each of the first set of data signals and the second set of data signals including data to be either read from or written to a memory array of the first memory device during the memory access operation.

An electronic system comprising:

an input device;
an output device;
a processing device coupled to the input device and the output device;
and
a memory system coupled to the processing device, the memory system comprising:
a first rank of memory chips;
a second rank of memory chips;
and
a circuitry coupled to the first rank and second rank of memory chips, the circuitry configured to:
transmit a first set of first data signals for a first memory access operation and a second set of the first data signals for the first memory access operation to or from the first rank of memory chips without requiring more than one reference change for the first set of the first data signals and the second set of the first data signals, each of the first set of first data signals and the second set of the first data signals including data to be either read from or written to a memory array of the first rank of memory chips during the first memory access operation;
and
transmit a first set of second data signals for a second memory access operation and a second set of the second data signals for the second memory access operation to or from the second rank of memory chips without requiring more than one reference change for the first set of the second data signals and the second set of the second data signals, each of the first set of second data signals and the second set of second data signals including data to be either read from or written to a memory array of the second rank of memory chips during the second memory access operation.

9 more elements

Dependencies are inferred from the claim text.

Facts

Application

16/448,541Filed 21 Jun 2019

Published

US 2020/0402547 A124 Dec 2020

Granted

31 Aug 2021

Term ends

Not estimatedThe source records don’t support an estimate.

Classification17 codes

G11C 5/063
Arrangements for interconnecting storage elements electrically, e.g. by wiring: voltage and signal distribution in integrated semi-conductor…
G11C 5/025
Disposition of storage elements, e.g. in the form of a matrix array: geometric lay-out considerations of storage- and peripheral-blocks in a…
G11C 5/04
Disposition of storage elements, e.g. in the form of a matrix array: supports for storage elements , e.g. memory modules; Mounting or fixing of…
G11C 7/10
Arrangements for writing information into, or reading information out from, a digital store: input/output [I/O] data interface arrangements, e.g.…

Transmitting data signals on separate layers of a memory module, and related methods, systems and apparatuses

Life of this patent

Transmitting data signals on separate layers of a memory module, and related methods, systems and apparatuses

Life of this patent

Abstract

Claims20