Display device with shift register segment start signal control in case of malfunction

A display device, comprising:

• a plurality of shift register segments;
• a monitor output wiring line connected to an output terminal of at least one shift register unit of a final shift register segment among the plurality of shift register segments;
• and
• a controller circuit,
• wherein each of the plurality of shift register segments is connected to a plurality of scan signal lines for a series of two or more pixels and has a start signal line independent of the other shift register segments,
• wherein the monitor output wiring line is connected to the plurality of shift register segments,
• wherein the controller circuit is configured to:
• identify a malfunction of at least one of the plurality of shift register segments by comparing a pulse signal output to the monitor output wiring line with a predetermined reference signal;
• and
• output a start signal in accordance with the identified malfunction,
• wherein the output terminal of the at least one shift register unit of the final shift register segment among the plurality of shift register segments is not connected to any of the plurality of scan signal lines, and
• wherein the start signal is input to one of the plurality of shift register segments at a timing when a carry signal is received by the at least one shift register unit of the final shift register segment among the plurality of shift register segments.

A display device, comprising:

• a display unit that includes,
• a plurality of scan signal lines;
• a plurality of video signal lines;
• a plurality of pixels arranged in a grid pattern in which each pixel includes a pixel electrode;
• a switching element connected to one of the plurality of scan signal lines, one of the plurality of video signal lines and the pixel electrode, and configured to turn on/off a video signal to the pixel electrode;
• a shift register connected to the plurality of scan signal lines and configured to output a pulse signal sequentially, the shift register being divided into a plurality of shift register segments, each shift register segment including a plurality of shift register units connected and spatially arranged in a sequential order and supplying scan signals to the plurality of scan signal lines, each of the plurality of shift register units including a final shift register unit having an output terminal;
• a clock signal line that supplies a clock signal to each of the plurality of shift register segments;
• a plurality of start signal lines that supply a plurality of start signals to each of the plurality of shift register segments;
• a driver configured to generate the clock signal to be supplied to each of the plurality of shift register segments, and the video signal to be supplied to the plurality of video signal lines;
• a monitor output wiring line connected to the output terminal of the final shift register unit of each of the plurality of the shift register segments;
• and
• a controller configured to monitor the output signal of the monitor output wiring line and detect a malfunction of any one of the plurality of shift register segments.