Shift register and method for driving the same, gate driving circuit and display device

A shift register, comprising:

• an input sub-circuit, an output sub-circuit, a reset sub-circuit, and a first shift output sub-circuit to an m-th shift output sub-circuit, m being an integer greater than or equal to 2, wherein:
• the input sub-circuit is connected with a first signal input terminal, a first clock signal terminal, a first node, a second node and a first power terminal, and is configured to supply a signal of the first signal input terminal to the first node under control of the first clock signal terminal;
• the output sub-circuit is connected with a second signal input terminal, a first signal output terminal, the first node, a third node and a second power terminal, and is configured to output a signal of the first node to the third node and a signal of the second signal input terminal to the first signal output terminal under control of the first node;
• the reset sub-circuit is connected with the first node, the second node, the third node, an m-th shift node, the second power terminal, an m-th shift signal output terminal and a third signal input terminal, and is configured to supply a signal of the second power terminal to the first node, the third node, the m-th shift node, and the m-th shift signal output terminal under control of the third signal input terminal;
• the first shift output sub-circuit is connected with the third node, a first shift node, a second clock signal terminal, the first power terminal and a first shift signal output terminal, and is configured to output a signal of the first power terminal to the first shift signal output terminal under control of the second clock signal terminal and in response to a signal of the third node;
• and
• an i-th shift output sub-circuit is connected with the third node, an (i−1)-th shift node, an i-th shift node, an (i+1)-th clock signal terminal, the first power terminal, the second power terminal, an (i−1)-th shift signal output terminal and an i-th shift signal output terminal, and is configured to output the signal of the first power terminal to the i-th shift signal output terminal under control of the (i+1)-th clock signal terminal and in response to the signal of the third node, and supply the signal of the second power terminal to the (i−1)-th shift signal output terminal and the (i−1)-th shift node under control of the (i+1)-th clock signal terminal, where i is an integer that is greater than or equal to 2 and less than or equal to m.