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US 11,107,263 B2Granted
Techniques to manage execution of divergent shaders
AssigneeIntel Corporation
InventorsJohn G. Gierach, Karthik Vaidyanathan, Thomas F. Raoux
Life of this patent
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Abstract
Examples are described here that can be used to enable a main routine to request subroutines or other related code to be executed with other instantiations of the same subroutine or other related code for parallel execution. A sorting unit can be used to accumulate requests to execute instantiations of the subroutine. The sorting unit can request execution of a number of multiple instantiations of the subroutine corresponding to a number of lanes in a SIMD unit. A call stack can be used to share information to be accessed by a main routine after execution of the subroutine completes.
Claims19
An apparatus comprising:
- at least one memory device;
- execution logic including a plurality of single instruction multiple data (SIMD) execution units;
- at least one processor configured to perform a thread scheduler and a sorting logic, wherein:
- the thread scheduler is to dispatch at least one thread for execution by at least a portion of the execution logic;
- the at least one thread is associated with a first shader, execution of the first shader is to cause a request to perform a first subroutine, and
- in response to the request to perform the first subroutine, the sorting logic is to request the thread scheduler to dispatch execution of a combination of the first subroutine with one or more other instances of the first subroutine based on an occurrence of a sooner of (i) a threshold number of requests to perform the first subroutine being met or (ii) expiration of a timer, wherein the timer is to measure an elapsed time from a time of receipt of the request to perform the first subroutine, wherein the at least one memory device is to store a table that comprises a collection of callable shader entry points and references to kernel locations in the at least one memory device, wherein the sorting logic is to dispatch the first shader and dispatch the combination of the first subroutine with one or more other instances of the first subroutine based on one or more locations in the at least one memory device specified by the table.
3 more elements
At least one non-transitory computer-readable medium comprising instructions stored thereon, that if executed by at least one processor, cause the at least one processor to:
- analyze a first shader to determine any branch with two divergent subroutines, the two divergent subroutines comprising a first subroutine and a second subroutine;
- form a function table comprising identification of the first shader, the first subroutine, and the second subroutine, wherein the function table comprises at least one callable shader entry point and at least one reference to a subroutine kernel location in at least one memory device;
- execute the first shader;
- execute the first subroutine in parallel with one or more instances of the first subroutine based on an occurrence of a sooner of (i) a threshold number of requests to perform the first subroutine being met or (ii) expiration of a timer, wherein the timer is to measure an elapsed time from a time of receipt of a request to perform the first subroutine, wherein the execution of the first shader and the first subroutine in parallel with one or more other instances of the first subroutine are based on at least one of the at least one callable shader entry point and at least one of the at least one reference to a subroutine kernel location in the at least one memory device;
- and
- execute the second subroutine in parallel with one or more instances of the second subroutine.
3 more elements
A system comprising:
- at least one memory;
- at least one processor;
- and
- at least one graphics processing unit communicatively coupled to the at least one memory and to the at least one processor, wherein:
- the at least one processor is to:
- request execution of a shader to process data stored in the at least one memory using a portion of the at least one graphics processing unit, the shader comprising a first subroutine and
- dispatch execution of a group comprising the first subroutine with one or more other instances of the first subroutine using a portion of the at least one graphics processing unit based on an occurrence of a sooner of (i) a threshold number of requests to perform the first subroutine being met or exceeded or (ii) expiration of a timer, wherein the timer is to measure an elapsed time from an oldest time of receipt of a first subroutine in the group, wherein the dispatch execution of the group comprising the first subroutine with one or more other instances of the first subroutine are based on one or more locations in the at least one memory specified by a table, wherein the table comprises a collection of callable shader entry points and references to subroutine kernel locations in the at least one memory.
4 more elements
Dependencies are inferred from the claim text.