Asymmetric multi-core heterogeneous parallel processing system with content aware and display aware rendering logic

An asymmetric multi-core heterogeneous graphics processing unit (GPU), comprising:

• a first group of GPU cores each having a first microarchitecture and a first power consumption profile, wherein the first group of GPU cores is configured to execute a first subset of an entire instruction set architecture (ISA);
• a second group of GPU cores each having a second microarchitecture and a second power consumption profile higher than the first power consumption profile, wherein the second group of GPU cores is configured to execute the entire ISA;
• a controller connected to the first group of GPU cores and the second group of GPU cores, wherein the controller is configured to receive, an ISA instruction of the ISA and determine whether the instruction should be executed by the first group of GPUs, or by the second group of GPUs;
• and
• wherein the ISA instruction is generated by an application programming interface (API), the API allowing an application to request the ISA instruction to be executed on the first group of GPU cores, or the second group of GPU cores, wherein the first group of GPU cores is distinct from the second group of GPU cores;
• and wherein the application determines a computational complexity of a rendered first object and generates ISA instructions to render the first object by the second group of GPU cores, and the second group of GPU cores is further configured to render the first object when the computational complexity rendering of the first object exceeds a first threshold in response to ISA instructions generated by the application.