Hardware architecture for processing data in neural network

An artificial intelligence accelerator for performing convolutional operations related to a neural network, the artificial intelligence accelerator comprising:

• a first data buffer configured to receive input data of a layer in the neural network and shift the input data slice by slice downstream, each slice having a predetermined size and dimension;
• a second data buffer configured to receive kernel data of the layer in the neural network and shift the kernel data slice by slice downstream;
• a first input shift register coupled to the first data buffer, the first input shift register having the size and dimension of the slice and configured to receive an input data slice from the first data buffer, the first input shift register comprising a two-dimensional shift register configured to shift values in the input data slice in a first direction and in a second direction;
• a second input shift register coupled to the second data buffer, the second input shift register having the size and dimension of the slice and configured to receive a kernel data slice from the second data buffer;
• a multiplication block circuit coupled to the first input shift register and the second input shift register, the multiplication block circuit configured to perform computations related to the convolutional operations between values in the input data slice and values in the kernel data slice;
• and
• an output buffer coupled to the multiplication block circuit, the output buffer configured to receive an output of the computations of the multiplication block circuit and pass the output back to the first data buffer as input data of a succeeding layer in the neural network.