Automation for monolithic 3D devices

A method of designing a 3D Integrated Circuit, the method comprising:

• performing partitioning to at least a logic strata comprising logic and a memory strata comprising memory;
• then
• performing a first placement of said logic strata using a 2D placer executed by a computer,
• wherein said 2D placer is a Computer Aided Design (CAD) tool for two-dimensional devices;
• and
• performing a second placement of said memory strata based on said first placement,
• wherein said logic comprises at least one decoder representation for said memory, and
• wherein said memory comprises at least a first memory and a second memory,
• wherein said first memory comprises a first memory decoder representation and said second memory comprises a second memory decoder representation,
• wherein said 2D placer is set so said second memory decoder representation is not placed within a rectangle defined by placement of said first memory decoder representation.

A method of designing a 3D Integrated Circuit, the method comprising:

• performing partitioning to at least a logic strata comprising logic and a memory strata comprising memory;
• then
• performing a first placement of said logic strata using a 2D placer executed by a computer,
• wherein said 2D placer is a Computer Aided Design (CAD) tool for two-dimensional devices;
• and
• performing a second placement of said memory strata based on said first placement,
• wherein said partitioning comprises a step of assigning at least one logic block to said memory strata for improved balancing of said logic strata area and said memory strata area.