Flexible constraint-based logic cell placement

A system comprising:

• a memory having computer readable instructions;
• and
• one or more processors for executing the computer readable instructions, the computer readable instructions controlling the one or more processors to perform operations comprising:
• determining a cell placement restriction rule for a first type of logic cell that specifies relative placement rules for one or more other cell types placed within a predetermined proximity to the first type of logic cell, the predetermined proximity comprising a number of pitches, the cell placement restriction rule comprising an offset requirement between the first type of logic cell and a second type of logic cell;
• responsive to placing a first cell comprising the first type of logic cell within a semiconductor layout, tagging the first cell with the cell placement restriction rule for the first type of logic cell;
• placing a second cell at an initial position within the semiconductor layout, wherein the second cell comprises the second type of logic cell;
• and
• determining whether any portion of the second cell is within the predetermined proximity of the first cell by considering an area around the first cell that is extended both horizontally and vertically by the predetermined number of pitches;
• responsive to determining that a portion of the second cell is within the predetermined proximity, applying the cell placement restriction rule to the second cell;
• and
• responsive to determining that the initial position of the second cell violates the cell placement restriction rule, repositioning the first cell or the second cell to a modified position within the semiconductor layout, wherein the modified position satisfies the cell placement restriction rule by positioning the first cell and the second cell in a relative manner that satisfies the offset requirement.

A computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by a computer processor to cause the computer processor to perform a method comprising:

• determining a cell placement restriction rule for a first type of logic cell that specifies relative placement rules for one or more other cell types placed within a predetermined proximity to the first type of logic cell, the predetermined proximity comprising a number of pitches, the cell placement restriction rule comprising an offset requirement between the first type of logic cell and a second type of logic cell;
• responsive to placing a first cell comprising the first type of logic cell within a semiconductor layout, tagging the first cell with the cell placement restriction rule for the first type of logic cell;
• placing a second cell at an initial position within the semiconductor layout, wherein the second cell comprises the second type of logic cell;
• determining whether any portion of the second cell is within the predetermined proximity of the first cell by considering an area around the first cell that is extended both horizontally and vertically by the predetermined number of pitches;
• responsive to determining that a portion of the second cell is within the predetermined proximity, applying the cell placement restriction rule to the second cell;
• and
• responsive to determining that the initial position of the second cell violates the cell placement restriction rule, repositioning the first cell or the second cell to a modified position within the semiconductor layout, wherein the modified position satisfies the cell placement restriction rule by positioning the first cell and the second cell in a relative manner that satisfies the offset requirement.