Side channel attack protection

A semiconductor chip comprising:

• a ROM;
• a memory controller coupled to the ROM;
• a random number generator coupled to the memory controller, wherein the random number generator is configured to generate a random number;
• and
• a number shuffler coupled to the random number generator and the memory controller, wherein the number shuffler is configured to generate a bit write order based on the random number, wherein the memory controller is configured to write bits of a secret word into the ROM according to the bit write order, wherein the bit write order corresponds to a non-sequential order of the bits of the secret word, wherein the memory controller is configured to perform the writing of the bits of the secret word in a number of write cycles that is greater than the number of bits in the secret word.

A method for securing a secret word during a read operation from a read-only memory (ROM) in a semiconductor chip, the method comprising:

• generating a random number internal to the semiconductor chip;
• generating a bit read order using the random number internal to the semiconductor chip;
• reading the secret word from the ROM according to the bit read order internal to the semiconductor chip;
• writing read bits to a first section of a memory register internal to the semiconductor chip, wherein the bit read order corresponds to a non-sequential order of the bits of the secret word;
• and
• writing one or more pseudo bits to a second section of the memory register in between writing two read bits of the secret word to the first section such that a number of read cycles to read the secret word from the ROM is greater than the number of bits in the secret word.