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US 11,106,623 B1Granted
Virtualized multicore systems with extended instruction heterogeneity
AssigneeOpen Invention Network, LLC
InventorRussell C. McKown
Life of this patent
Estimating the term…
Abstract
A system on a chip may include a plurality of data plane processor cores sharing a common instruction set architecture. At least one of the data plane processor cores is specialized to perform a particular function via extensions to the otherwise common instruction set architecture. Such systems on a chip may have reduced physical complexity, cost, and time-to-market, and may provide improvements in core utilization and reductions in system power consumption.
Claims19
A computer-implemented method performed by a physical computing device, the computer-implemented method comprising:
- identifying a set of extended instructions of a common instruction set architecture (ISA) for processing a task which are executable by a first data plane processing core;
- migrating a task from the first data plane processing core to perform load balancing between the first data plane processing core and a second data plane processing core;
- determining equivalent processing instructions for the task from a different set of instructions of the common ISA which are executable by the second data plane processing core, and
- executing, by the second data plane processing core, the equivalent processing instructions from the different set of instructions of the common ISA to produce computational results that are equivalent to the set of extended instructions of the common ISA executable by the first data plane processing core;
- wherein synchronization markers are inserted into a copy of examined source code and into associated executable code for the first and second data plane processing cores output from compilers of the first and second data plane processing cores;
- wherein the synchronization markers are used to bound code segments of interest for localization of extended instructions for the first data plane processing core.
3 more elements
A computer-implemented method performed by a physical computing device, the computer-implemented method comprising:
- searching code for a synchronization marker;
- in response to a synchronization marker being found, determining code segments corresponding to the synchronization marker that contain extended instructions of a common instruction set architecture (ISA) which are executable by a first data plane processing core;
- migrating a task from the first data plane processing core to perform load balancing between the first data plane processing core and a second data plane processing core;
- determining equivalent processing instructions for the task from a different set of instructions of the common ISA which are executable by the second data plane processing core;
- and
- outputting the equivalent processing instructions for processing the task from the common ISA to the second data plane processing core;
- identifying Extended Instructions to Equivalent Instructions (EI2EI) segments of interest which comprises parsing the code segments of the first data plane processing core and the second data plane processing core to identify regions of code following a given extended instruction of the first data plane processing core that are equivalent until an ending synchronization marker,
- wherein the synchronization marker is used to bound code segments of interest for localization of extended instructions for the first data plane processing core.
5 more elements
A non-transitory computer readable medium comprising instructions, that when read by a processor, cause the processor to perform:
- identifying a set of extended instructions of a common instruction set architecture (ISA) for processing a task which are executable by a first data plane processing core;
- migrating a task from the first data plane processing core to perform load balancing between the first data plane processing core and a second data plane processing core;
- determining equivalent processing instructions for the task from a different set of instructions of the common ISA which are executable by the second data plane processing core, and
- executing, by the second data plane processing core, the equivalent processing instructions from the different set of instructions of the common ISA to produce computational results that are equivalent to the set of extended instructions of the common ISA executable by the first data plane processing core;
- wherein synchronization markers are inserted into a copy of examined source code and into associated executable code for the first and second data plane processing cores output from compilers of the first and second data plane processing cores;
- wherein the synchronization markers are used to bound code segments of interest for localization of extended instructions for the first data plane processing core.
3 more elements
Dependencies are inferred from the claim text.