Transmission of synchronous data via a serial data bus, in particular a SPI bus

A serial data bus for transmitting synchronous data between a master communication module and a slave communication module, comprising:

• a clock (CLK) wire, a Master Input Slave Output (MISO) signal wire, and a Master Output Slave Input (MOSI) signal wire,
• wherein the master communication module transmits to the slave communication module, on the MOSI signal wire, a first frame that encapsulates a first portion of the synchronous data,
• wherein the slave communication module transmits to the master communication module, on the MISO signal wire, a second frame that encapsulates a second portion of the synchronous data,
• wherein the first frame and the second frame each comprises a frame identifier,
• wherein the first frame and the second frame are simultaneously exchanged and checked between the master and slave communication modules according to at least one predetermined sequencing corresponding to a unique pairing of the frame identifiers of the two simultaneously exchanged frames,
• wherein an integrity of the transmission in each of the two master and slave communication modules is checked on the basis of an extraction of the frame identifier of the two simultaneously exchanged frames according to said at least one predetermined sequencing and is calculated, in each of the two master and slave communication modules, a time period separating two successively received frames and comparing the calculated time period with at least one expected predetermined inter-frame period;
• and
• wherein any transmission of frames from one of the two master or slave communication modules is interrupted during an interruption time period greater than said at least one expected inter-frame period, following any communication error detected during checking of the transmission integrity.

A motor vehicle, comprising:

• a master communication module, a slave communication module, and a serial data bus for transmitting synchronous data between the master communication module and the slave communication module,
• wherein the serial data bus comprises a clock (CLK) wire, a Master Input Slave Output (MISO) signal wire, and a Master Output Slave Input (MOSI) signal wire,
• wherein the master communication module transmits to the slave communication module, on the MOSI signal wire, a first frame that encapsulates a first portion of the synchronous data,
• wherein the slave communication module transmits to the master communication module, on the MISO signal wire, a second frame that encapsulates a second portion of the synchronous data,
• wherein the first frame and the second frame each comprise a frame identifier,
• wherein the first frame and the second frame are simultaneously exchanged and checked between the master and slave communication modules according to at least one predetermined sequencing corresponding to a unique pairing of the frame identifiers of the two simultaneously exchanged frames,
• wherein an integrity of the transmission in each of the two master and slave communication modules is checked on the basis of an extraction of the frame identifier of the two simultaneously exchanged frames according to said at least one predetermined sequencing and is calculated, in each of the two master and slave communication modules, a time period separating two successively received frames and comparing the calculated time period with at least one expected predetermined inter-frame period;
• and
• wherein any transmission of frames from one of the two master or slave communication modules is interrupted during an interruption time period greater than said at least one expected inter-frame period, following any communication error detected during checking of the transmission integrity.