Synchronizing access to shared memory by extending protection for a target address of a store-conditional request

A processing unit for a data processing system including multiple processing units all communicably coupled to a shared system memory via a system interconnect, said processing unit comprising:

• a processor core that executes memory access instructions including a store-conditional instruction, wherein execution of the store-conditional instruction generates a store-conditional request that specifies a store target address and store data;
• a reservation register that records shared memory addresses for which the processor core has obtained reservations;
• and
• a cache that services the store-conditional request by conditionally updating the shared memory with the store data based on the reservation register indicating a reservation for the store target address, wherein the cache includes a state machine configured to protect the store target address against access by any conflicting memory access request snooped on the system interconnect during a protection window extension following servicing of the store-conditional request, wherein the cache is configured to vary a duration of the protection window extension for different snooped memory access requests based on one of broadcast scopes of the snooped memory access requests on the system interconnect and locations of masters of the snooped memory access requests relative to the processing unit.