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US 11,106,604 B2Granted
Variable read latency on a serial memory bus
AssigneeCypress Semiconductor Corporation
InventorClifford Zitlaw
Life of this patent
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Abstract
Example apparatus, systems, and methods receive a request for data associated with an address and responsively access a memory array to obtain the data. Embodiments transition a bus from a first state to a second state and after the transitioning of the bus, drive the data onto the bus.
Claims8
A method comprising:
- receiving a request for data associated with an address via a bus, wherein the bus is driven to a first state after the request;
- responsive to the request, accessing a memory array of a memory device to obtain the data, wherein the bus is driven to maintain at the first state at least partly by the memory device during an entire period of the accessing the memory array;
- transitioning the bus from the first state to a second state;
- and
- after the transitioning of the bus, driving the data onto the bus.
2 more elements
Dependencies are inferred from the claim text.